公开(公告)号：US20140145259A1

公开(公告)日：2014-05-29

申请号：US14169627

申请日：2014-01-31

Applicant: HITACHI ULSI SYSTEMS CO., LTD. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20150179763A1

公开(公告)日：2015-06-25

申请号：US14624987

申请日：2015-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20130126965A1

公开(公告)日：2013-05-23

申请号：US13739494

申请日：2013-01-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.