公开(公告)号：US20230387219A1

公开(公告)日：2023-11-30

申请号：US18185079

申请日：2023-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Futoshi KOMATSU ,  Tomoo NAKAYAMA ,  Katsuhiro UCHIMURA ,  Hiroshi INAGAWA

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/56 ,  H01L21/288

CPC classification number: H01L29/401 ,  H01L29/66348 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02359 ,  H01L21/304 ,  H01L21/56 ,  H01L21/288 ,  H01L29/4236

Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.

公开(公告)号：US20140145259A1

公开(公告)日：2014-05-29

申请号：US14169627

申请日：2014-01-31

Applicant: HITACHI ULSI SYSTEMS CO., LTD. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20210225789A1

公开(公告)日：2021-07-22

申请号：US17225639

申请日：2021-04-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi TONEGAWA ,  Hiroshi INAGAWA

IPC: H01L23/00 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L29/861 ,  H01L29/45 ,  H01L23/495

Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.

公开(公告)号：US20160111490A1

公开(公告)日：2016-04-21

申请号：US14976873

申请日：2015-12-21

Applicant: RENESAS ELECTRONICS CORPORATION ,  Renesas Eastern Japan Semiconductor, Inc.

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OISHI

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20150179763A1

公开(公告)日：2015-06-25

申请号：US14624987

申请日：2015-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20140110780A1

公开(公告)日：2014-04-24

申请号：US14143196

申请日：2013-12-30

Applicant: Renesas Eastern Japan Semiconductor, Inc. ,  Renesas Electronics Corporation

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OISHI

IPC: H01L29/78

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract translation: 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20130137223A1

公开(公告)日：2013-05-30

申请号：US13747557

申请日：2013-01-23

Applicant: Renesas Electronics Corporation ,  Hitachi Tobu Semiconductor, Ltd.

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OISHI

IPC: H01L29/66

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20130126965A1

公开(公告)日：2013-05-23

申请号：US13739494

申请日：2013-01-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.