公开(公告)号：US20240204098A1

公开(公告)日：2024-06-20

申请号：US18592332

申请日：2024-02-29

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20210074816A1

公开(公告)日：2021-03-11

申请号：US16996351

申请日：2020-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20160111490A1

公开(公告)日：2016-04-21

申请号：US14976873

申请日：2015-12-21

Applicant: RENESAS ELECTRONICS CORPORATION ,  Renesas Eastern Japan Semiconductor, Inc.

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OISHI

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210217888A1

公开(公告)日：2021-07-15

申请号：US17216136

申请日：2021-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20250015138A1

公开(公告)日：2025-01-09

申请号：US18892925

申请日：2024-09-23

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20140145259A1

公开(公告)日：2014-05-29

申请号：US14169627

申请日：2014-01-31

Applicant: HITACHI ULSI SYSTEMS CO., LTD. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OOISHI

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66734 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/76897 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract translation: 半导体器件具有沟槽栅极结构的FET，其通过在半导体衬底的主表面中延伸的沟槽中设置作为栅极的导电层而获得，其中沟槽栅极导电层的上表面是 形成为等于或高于半导体衬底的主表面。 沟槽栅极的导电层形成为具有基本平坦或凹入的上表面，并且上表面形成为等于或高于半导体衬底的主表面。 在蚀刻半导体衬底以形成沟槽栅极的导电层的上表面之后，通过离子注入形成沟道区域和源极区域，使得半导体器件不发生源极偏移。

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20210159315A1

公开(公告)日：2021-05-27

申请号：US17068378

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

Abstract: To improve an on-resistance of a semiconductor device. A plurality of collector regions are formed at a predetermined interval on a bottom surface of a drift layer made of SiC. Next, on the bottom surface of the drift layer, both of the drift layer and a collector region via a silicide layer are connected to a collector electrode.