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    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    1.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权

    公开(公告)号：US20210294691A1

    公开(公告)日：2021-09-23

    申请号：US16821915

    申请日：2020-03-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsushige MATSUBARA ,  Ryoji HASHIMOTO ,  Takahiro IRITA ,  Kenichi SHIMADA ,  Tetsuya SHIBAYAMA

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30

    Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

    SEMICONDUCTOR DEVICE AND ACCESS CONTROL METHOD
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND ACCESS CONTROL METHOD 有权

    公开(公告)号：US20210141749A1

    公开(公告)日：2021-05-13

    申请号：US17150565

    申请日：2021-01-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsuya MIZUMOTO ,  Toshiyuki HIRAKI ,  Nobuhiko HONDA ,  Sho YAMANAKA ,  Takahiro IRITA ,  Yoshihiko HOTTA

    IPC: G06F13/16 ,  G06F13/362 ,  G06F13/18

    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170270063A1

    公开(公告)日：2017-09-21

    申请号：US15127765

    申请日：2015-10-01

    Applicant: Renesas Electronics Corporation

    Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

    IPC: G06F13/16 ,  G11C11/406 ,  G06F13/40

    CPC classification number: G06F13/1673 ,  G06F13/1605 ,  G06F13/362 ,  G06F13/4068 ,  G11C11/406

    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

    INFORMATION PROCESSING DEVICE AND MOBILE TERMINAL
    8.
    发明申请
    INFORMATION PROCESSING DEVICE AND MOBILE TERMINAL 审中-公开
    信息处理设备和移动终端

    公开(公告)号：US20150036677A1

    公开(公告)日：2015-02-05

    申请号：US14516644

    申请日：2014-10-17

    Applicant: Renesas Electronics Corporation

    Inventor： Yutaka UCHIMURA ,  Takahiro IRITA ,  Jiro HARA

    IPC: H04W56/00

    CPC classification number: H04W56/003 ,  G10L19/16 ,  H04L29/06

    Abstract: There is a need to enable decompression of a speech signal even if no network synchronizing signal is output from a baseband processing portion. For this purpose, an information processing device includes a first serial interface. The first serial interface includes a notification signal generation circuit that generates a notification signal each time compressed data incorporated from the baseband processing portion reaches a predetermined data quantity, and notifies a speech processing portion of this state using the notification signal. The speech processing portion includes a synchronizing signal generation circuit that generates a network synchronizing signal based on the notification signal. A clock signal for PCM communication is generated based on the network synchronizing signal. A speech signal can be decompressed even if no network synchronizing signal is output from the baseband processing portion.

    Abstract translation: 即使没有从基带处理部分输出网络同步信号，也需要能够对语音信号进行解压缩。 为此，信息处理装置包括第一串行接口。 第一串行接口包括每当从基带处理部分合并的压缩数据达到预定数据量时产生通知信号的通知信号生成电路，并使用通知信号通知语音处理部分。 语音处理部分包括基于通知信号产生网络同步信号的同步信号发生电路。 基于网络同步信号产生用于PCM通信的时钟信号。 即使没有从基带处理部分输出网络同步信号，也可以解压缩语音信号。

    SEMICONDUCTOR DEVICE AND STARTUP CONTROL METHOD FOR SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND STARTUP CONTROL METHOD FOR SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240143465A1

    公开(公告)日：2024-05-02

    申请号：US18452305

    申请日：2023-08-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kiyoshi HAYASE ,  Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Kyohei YAMAGUCHI ,  Takahiro IRITA ,  Shinichi SHIBAHARA

    IPC: G06F11/22

    CPC classification number: G06F11/2284

    Abstract: A semiconductor device includes first and second processor cores configured to perform a lock step operation and including first and second scan chains. The semiconductor device further includes a scan test control unit that controls a scan test of the first and second processor cores using the first and second scan chains, and a start-up control unit that outputs a reset signal for bringing the first and second processor cores into a reset state. The start-up control unit outputs an initialization scan request before the start of a lock step operation, and the scan test control unit performs an initialization scan test operation on the first and second processor cores by using an initialization pattern.

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