公开(公告)号：US20150228341A1

公开(公告)日：2015-08-13

申请号：US14691125

申请日：2015-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya WATANABE ,  Isamu HAYASHI ,  Teruhiko AMANO ,  Fukashi MORISHITA ,  Kenji YOSHINAGA ,  Mihoko AKIYAMA ,  Shinya MIYAZAKI ,  Masakazu ISHIBASHI ,  Katsumi DOSAKA

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。