公开(公告)号：US20180149831A1

公开(公告)日：2018-05-31

申请号：US15884726

申请日：2018-01-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KITAMORI ,  Katsumi DOSAKA ,  Fumihide MURAO

IPC: G02B7/36 ,  H04N5/3745 ,  H04N5/374 ,  G02B7/30 ,  H01L27/146 ,  H04N5/369

CPC classification number: G02B7/365 ,  G02B7/30 ,  H01L27/14627 ,  H04N5/3696 ,  H04N5/3742 ,  H04N5/37457

Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

公开(公告)号：US20150228341A1

公开(公告)日：2015-08-13

申请号：US14691125

申请日：2015-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya WATANABE ,  Isamu HAYASHI ,  Teruhiko AMANO ,  Fukashi MORISHITA ,  Kenji YOSHINAGA ,  Mihoko AKIYAMA ,  Shinya MIYAZAKI ,  Masakazu ISHIBASHI ,  Katsumi DOSAKA

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US20130112852A1

公开(公告)日：2013-05-09

申请号：US13661724

申请日：2012-10-26

Applicant: Renesas Electronics Corporation

Inventor： Shunsuke KIZUNA ,  Katsumi DOSAKA ,  Hiroto UTSUNOMIYA

IPC: H04N5/378

CPC classification number: H04N5/378

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.

Abstract translation: 固态图像拾取装置包括实现更高精度和更高速度转换的列ADC。 转换器通过顺序地执行第一至第N（三个或三个以上的整数）转换级，将通过相应垂直读取线的每个像素输出的信号转换为数字值。 在第一到第（N-1）个转换级中，每个转换器通过将保持级的电压与参考电压进行比较来确定包括数字值的最高有效位的高位数值，同时改变保持节点处的电压 。 在第N次转换阶段，每个转换器通过将保持节点处的电压与参考电压进行比较来确定剩余比特到最低有效位的值，同时在保持节点的电压步长范围内连续改变电压 （N-1）转换级或超出范围的范围。

公开(公告)号：US20160227143A1

公开(公告)日：2016-08-04

申请号：US14961630

申请日：2015-12-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KITAMORI ,  Katsumi DOSAKA ,  Fumihide MURAO

IPC: H04N5/378 ,  H04N5/372 ,  G02B7/36 ,  H04N5/369

CPC classification number: G02B7/365 ,  G02B7/30 ,  H01L27/14627 ,  H04N5/3696 ,  H04N5/3742 ,  H04N5/37457

Abstract: In an image sensor according to related art, charge information cannot be read at the same time from a pair of photoelectric conversion elements placed corresponding to one microlens. According to one embodiment, an image sensor includes a first photoelectric conversion element and a second photoelectric conversion element placed corresponding to one microlens, a first transfer transistor placed corresponding to the first photoelectric conversion element and a second transfer transistor placed corresponding to the second photoelectric conversion element, a read timing signal line that supplies a common read timing signal to the first transfer transistor and the second transfer transistor, a first output line that outputs a signal of the first photoelectric conversion element to the outside, and a second output line that outputs a signal of the second photoelectric conversion element to the outside.

Abstract translation: 在根据现有技术的图像传感器中，不能同时从对应于一个微透镜放置的一对光电转换元件读取电荷信息。 根据一个实施例，图像传感器包括对应于一个微透镜放置的第一光电转换元件和第二光电转换元件，对应于第一光电转换元件放置的第一转移晶体管和与第二光电转换相对应放置的第二转移晶体管 元件，向第一传输晶体管和第二传输晶体管提供公共读定时信号的读定时信号线，将第一光电转换元件的信号输出到外部的第一输出线和输出 第二光电转换元件的信号到外部。

公开(公告)号：US20160212367A1

公开(公告)日：2016-07-21

申请号：US15082913

申请日：2016-03-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/3745 ,  H04N5/376 ,  H03M1/66 ,  H04N5/378

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20150124134A1

公开(公告)日：2015-05-07

申请号：US14591871

申请日：2015-01-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Zenzo SUZUKI ,  Katsumi DOSAKA

IPC: H04N5/3745 ,  H04N5/355 ,  H04N5/347

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14641 ,  H01L27/14645 ,  H04N5/335 ,  H04N5/347 ,  H04N5/3559 ,  H04N5/37452 ,  H04N5/37457 ,  H04N5/378

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

Abstract translation: 提供了一种能够实现高图像质量和宽动态范围的图像拾取装置。 包括在图像拾取装置中的每个像素单元包括：四个光电二极管; 四个传输晶体管; 用于存储在光电二极管处产生的电荷的电荷存储部分（四个浮动扩散）; 放大晶体管; 选择晶体管; 和复位晶体管。 图像拾取装置还包括多个耦合晶体管。 每个耦合晶体管将像素单元的两个像素单元的电荷存储部分耦合在一起。 扫描电路根据读取模式来接通或关闭耦合晶体管。

公开(公告)号：US20170162615A1

公开(公告)日：2017-06-08

申请号：US15438265

申请日：2017-02-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Zenzo SUZUKI ,  Katsumi DOSAKA

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/3745

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14641 ,  H01L27/14645 ,  H04N5/335 ,  H04N5/347 ,  H04N5/3559 ,  H04N5/37452 ,  H04N5/37457 ,  H04N5/378

Abstract: An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.

公开(公告)号：US20140226049A1

公开(公告)日：2014-08-14

申请号：US14256680

申请日：2014-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/369

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

公开(公告)号：US20170026594A1

公开(公告)日：2017-01-26

申请号：US15145752

申请日：2016-05-03

Applicant: Renesas Electronics Corporation

Inventor： Koji SHIDA ,  Hideki WAKISAKA ,  Katsumi DOSAKA

IPC: H04N5/355 ,  H04N5/378 ,  H04N5/235

CPC classification number: H04N5/35581 ,  H04N5/2355

Abstract: According to one aspect of the present invention, an image sensor and a sensor module have a configuration in which the image sensor outputs first brightness information representing brightness information of first image information obtained with a first exposure time and second brightness information representing brightness information of second image information obtained with a second exposure time separately from a composite image obtained by synthesizing the first image information and the second image information, updates the first and second exposure times based on an exposure time set value externally generated based on the first brightness information and the second brightness information, and changes a synthesis set value used for synthesis of the composite image based on the exposure time set value externally generated based on the first brightness information and the second brightness information.

Abstract translation: 根据本发明的一个方面，图像传感器和传感器模块具有以下结构：图像传感器输出表示以第一曝光时间获得的第一图像信息的亮度信息的第一亮度信息和表示第二曝光时间的亮度信息的第二亮度信息 以与通过合成第一图像信息和第二图像信息而获得的合成图像分开的第二曝光时间获得的图像信息，基于根据第一亮度信息从外部生成的曝光时间设定值来更新第一和第二曝光时间， 并且基于根据第一亮度信息和第二亮度信息从外部生成的曝光时间设定值，改变用于合成图像合成的合成设定值。

公开(公告)号：US20150288904A1

公开(公告)日：2015-10-08

申请号：US14746030

申请日：2015-06-22

Applicant: Renesas Electronics Corporation

Inventor： SHUNSUKE KIZUNA ,  Katsumi DOSAKA ,  Hiroto UTSUNOMIYA

IPC: H04N5/378

CPC classification number: H04N5/378

Abstract: A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range.

Abstract translation: 固态图像拾取器件包括实现更高精度和更高速度转换的列ADC。 转换器通过顺序地执行第一至第N（三个或三个以上的整数）转换级，将通过相应垂直读取线的每个像素输出的信号转换为数字值。 在第一到第（N-1）个转换级中，每个转换器通过将保持级的电压与参考电压进行比较来确定包括数字值的最高有效位的高位数值，同时改变保持节点处的电压 。 在第N次转换阶段，每个转换器通过将保持节点处的电压与参考电压进行比较来确定剩余比特到最低有效位的值，同时在保持节点的电压步长范围内连续改变电压 （N-1）转换级或超出范围的范围。