公开(公告)号：US11262500B2

公开(公告)日：2022-03-01

申请号：US16700580

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Seigo Namioka ,  Tomoo Nakayama

IPC: G02B6/122 ,  G02B6/13 ,  G02F1/025 ,  G02B6/12

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

公开(公告)号：US11002997B2

公开(公告)日：2021-05-11

申请号：US16722394

申请日：2019-12-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seigo Namioka ,  Yasutaka Nakashiba

IPC: G02F1/025

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.

公开(公告)号：US11322668B2

公开(公告)日：2022-05-03

申请号：US16811910

申请日：2020-03-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seigo Namioka ,  Yasutaka Nakashiba

IPC: H01L33/58 ,  H01S5/026 ,  H01L25/16 ,  H01L33/00

Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.

公开(公告)号：US09305925B2

公开(公告)日：2016-04-05

申请号：US14531336

申请日：2014-11-03

Applicant: Renesas Electronics Corporation

Inventor： Seigo Namioka

IPC: H01L27/108 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L27/10814 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10894 ,  H01L29/4175 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR1. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.

Abstract translation: 为了实现eDRAM的高速操作，eDRAM包括：具有用作字线的栅电极，源极区和漏极区的选择MISFET; 源极电极，其耦合到所述源极区域; 以及连接到漏区DR1的排水塞电极。 eDRAM还包括：电容式插头电极，其联接到排水塞电极; 耦合到源极插头电极的位线; 覆盖位线的阻挡膜; 以及形成在所述阻挡膜上并具有第一电极，电介质膜和第二电极的电容元件。 第一电极耦合到电容式插头电极，并且电容式插头电极和位线的高度彼此相等。