公开(公告)号：US20130134549A1

公开(公告)日：2013-05-30

申请号：US13725389

申请日：2012-12-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuma ONISHI ,  Yoshitaka OTSU ,  Hiroshi KIMURA ,  Tetsuya NITTA ,  Shinichiro YANAGI ,  Katsumi MORII

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract translation: 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体衬底的表面上完成包括源极区和漏极区的高击穿电压横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US20130134510A1

公开(公告)日：2013-05-30

申请号：US13686900

申请日：2012-11-27

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro YANAGI

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

Abstract: In the interior of a semiconductor substrate having a main surface, a first p− epitaxial region is formed, a second p− epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p− epitaxial region and the second p− epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p− epitaxial region is formed between the n+ buried region and the second p− epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Abstract translation: 在具有主表面的半导体衬底的内部，形成第一p-外延区，在主表面侧形成第二p-外延区，并且n型漂移区和p型体区为 形成在主表面侧。 在第一p-外延区和第二p-外延区之间形成n +掩埋区，以便电隔离这些区。 在n +掩埋区域和第二p-外延区域之间形成具有高于第二p-外延区域的p型杂质浓度的p +掩埋区域。 p +掩埋区域至少位于n型漂移区域和p型体区域之间的接合处的下方，以避免紧邻与n型漂移区域接触的漏极区域下方的位置。