公开(公告)号：US20160027925A1

公开(公告)日：2016-01-28

申请号：US14875747

申请日：2015-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract translation: 半导体器件具有p型金属氧化物半导体层; 与p型金属氧化物半导体层连接的源电极; 与p型金属氧化物半导体层连接的漏电极; 以及与p型金属氧化物半导体层的一部分相对配置的栅电极。 栅电极和漏电极在顶视图中彼此分离。

公开(公告)号：US20160240564A1

公开(公告)日：2016-08-18

申请号：US15139782

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.