公开(公告)号：US20130168817A1

公开(公告)日：2013-07-04

申请号：US13670138

申请日：2012-11-06

Applicant: Renesas Electronics Corporation

Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。

公开(公告)号：US20140357047A1

公开(公告)日：2014-12-04

申请号：US14458976

申请日：2014-08-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Jun KAWAHARA ,  Naoya INOUE ,  Naoya FURUTAKE ,  Yoshihiro HAYASHI

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L2924/0002 ,  Y10S257/904 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract translation: 半导体器件包括：第一绝缘层（层间绝缘层），设置在第一绝缘层（层间绝缘层）上的电阻元件，至少其表面层为TaSiN层;以及层间绝缘层， 第一绝缘层（层间绝缘层）和电阻元件。 在层间绝缘层中设置多个具有与TaSiN层结合的端子的通孔塞。

公开(公告)号：US20160276026A1

公开(公告)日：2016-09-22

申请号：US14962777

申请日：2015-12-08

Applicant: Renesas Electronics Corporation

Inventor： Takashi HASE ,  Naoya FURUTAKE ,  Koji MASUZAKI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.

Abstract translation: 当写入ReRAM单元时，追求将单元设置在足够高或低电阻状态，同时防止过度写入。 公开了一种包括存储单元的半导体存储装置，每个存储单元包括可变电阻元件，以及控制电路，其执行将写入脉冲施加到存储器单元以将其变为高电阻状态的关闭写入处理以及应用于On 写入脉冲将其变为低电阻状态。 当存储单元置于低电阻状态时，控制电路在施加关闭写入脉冲之后，施加读取脉冲以进行读取的验证处理是否处于高电平或低电阻状态。 如果作为验证处理的结果，存储单元未被置于高电阻状态，则控制电路施加包括在写入脉冲中的复位脉冲，施加具有扩展脉冲宽度的关闭写入脉冲，并按照上述顺序执行验证处理。

公开(公告)号：US20160027925A1

公开(公告)日：2016-01-28

申请号：US14875747

申请日：2015-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L29/786 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract translation: 半导体器件具有p型金属氧化物半导体层; 与p型金属氧化物半导体层连接的源电极; 与p型金属氧化物半导体层连接的漏电极; 以及与p型金属氧化物半导体层的一部分相对配置的栅电极。 栅电极和漏电极在顶视图中彼此分离。

公开(公告)号：US20170309336A1

公开(公告)日：2017-10-26

申请号：US15646933

申请日：2017-07-11

Applicant: Renesas Electronics Corporation

Inventor： Takashi HASE ,  Naoya FURUTAKE ,  Koji MASUZAKI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.

公开(公告)号：US20160240564A1

公开(公告)日：2016-08-18

申请号：US15139782

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Kishou KANEKO ,  Naoya FURUTAKE ,  Shinobu SAITOU ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/477 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L27/1225 ,  H01L21/477 ,  H01L21/8254 ,  H01L27/0922 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/242 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/812

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.