公开(公告)号：US11415666B2

公开(公告)日：2022-08-16

申请号：US16585924

申请日：2019-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Oshima ,  Tetsuo Matsui ,  Mitsuya Fukazawa ,  Katsuki Tateyama ,  Masaki Fujiwara

IPC: G01S7/35 ,  H03M3/00 ,  G01S13/34

Abstract: A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

公开(公告)号：US09559716B1

公开(公告)日：2017-01-31

申请号：US15197447

申请日：2016-06-29

Applicant: Renesas Electronics Corporation

Inventor： Tetsuo Matsui ,  Hiroto Suzuki ,  Masaki Fujiwara ,  Tetsuro Matsuno

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/46 ,  H03M1/069 ,  H03M1/1061 ,  H03M1/124 ,  H03M1/468

Abstract: A processing speed can be improved while the accuracy of AD conversion is enhanced. An AD converter includes: a higher-order DAC that samples an analog input signal and performs DA conversion corresponding to higher-order bits of a digital output signal; an extension DAC that performs DA conversion to positive and negative polarities on an extension bit for expanding bits of the higher-order DAC; a lower-order DAC that performs DA conversion corresponding to lower-order bits of the digital output signal; a comparator that compares a comparison reference voltage with output voltages of the higher-order DAC, the extension DAC, and the lower-order DAC; and a successive approximation logic that controls successive approximation performed by the higher-order DAC, the extension DAC, and the lower-order DAC based on a comparison result of the comparator and generates the digital output signal.

Abstract translation: 可以提高处理速度，同时提高AD转换的精度。 AD转换器包括：高阶DAC，其对模拟输入信号进行采样，并对数字输出信号的高位进行DA转换; 扩展DAC，用于在用于扩展高阶DAC的位的扩展位上执行DA转换为正极性和负极性; 执行对应于数字输出信号的低阶位的DA转换的低阶DAC; 将比较参考电压与高阶DAC，扩展DAC和低阶DAC的输出电压进行比较的比较器; 以及基于比较器的比较结果控制由高阶DAC，扩展DAC和低阶DAC执行的逐次逼近的逐次逼近逻辑，并产生数字输出信号。

公开(公告)号：US10707894B2

公开(公告)日：2020-07-07

申请号：US15900598

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Oshima ,  Tetsuo Matsui ,  Mitsuya Fukazawa ,  Tomohiko Yano

IPC: H03M3/00 ,  H03H21/00 ,  G01S13/02 ,  G01S7/35

Abstract: A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.

公开(公告)号：US10903847B2

公开(公告)日：2021-01-26

申请号：US16717070

申请日：2019-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuo Matsui ,  Keisaku Sento ,  Tomohiko Ebata

IPC: H03M1/12 ,  H03M1/46

Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit 30 of a capacitance distribution type, a second digital-to-analog conversion circuit 31 of a capacitance distribution type, and a comparison circuit 32 for comparing output voltages of the two digital-to-analog conversion circuits, and before performing a successive comparison operation for successively changing a reference voltage applied to the first digital-to-analog conversion circuit, generates an intermediate digital value having a digital value corresponding to a voltage value of an analog input signal, determines a reference voltage to be applied to the second digital-to-analog conversion circuit 31 in accordance with the intermediate digital value, and thereafter performs a successive comparison operation using the first digital-to-analog conversion circuit 30 in a state in which the state of the second digital-to-analog conversion circuit 31 is held.