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公开(公告)号：US10051280B2
公开(公告)日：2018-08-14
申请号：US14928735
申请日：2015-10-30
Applicant: Renesas Electronics Corporation
Inventor： Seiji Mochizuki , Toshiyuki Kaya , Hiroshi Ueda , Tetsuya Shibayama
Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.
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公开(公告)号：US20150092840A1
公开(公告)日：2015-04-02
申请号：US14505369
申请日：2014-10-02
Applicant: Renesas Electronics Corporation
Inventor： Seiji Mochizuki , Tetsuya Shibayama
IPC: H04N19/126 , H04N19/593
CPC classification number: H04N19/126 , H04N19/115 , H04N19/124 , H04N19/146 , H04N19/149 , H04N19/152 , H04N19/176 , H04N19/50 , H04N19/593
Abstract: The present invention provides a video encoder and a method of operating the video encoder to implement high-precision bit rate control by reducing the risk of overflow of an intermediate buffer coupled between a quantizer and an encoding section. The intermediate buffer supplies a selection control signal indicative of whether the amount of stored data is large or small to a selector. If the selection control signal indicates large, the selector outputs an estimated code amount from a code amount estimation section to the rate controller. If the selection control signal indicates small, the selector outputs an actual code amount from the encoding section to the rate controller. The rate controller calculates the quantization scale according to the output of the selector and feedbacks the calculated quantization scale to the quantizer. The quantizer adjusts the quantizer scale.
Abstract translation: 本发明提供了一种视频编码器和一种操作视频编码器以通过减少耦合在量化器和编码部分之间的中间缓冲器溢出的风险来实现高精度比特率控制的方法。 中间缓冲器向选择器提供指示存储的数据量是大还是小的选择控制信号。 如果选择控制信号指示较大，则选择器将代码量估计部分的估计代码量输出到速率控制器。 如果选择控制信号指示较小，则选择器将编码部分的实际代码量输出到速率控制器。 速率控制器根据选择器的输出计算量化比例，并将计算出的量化比例反馈给量化器。 量化器调整量化器刻度。
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公开(公告)号：US10419663B2
公开(公告)日：2019-09-17
申请号：US15421503
申请日：2017-02-01
Applicant: Renesas Electronics Corporation
Inventor： Tetsuya Shibayama , Toshiyuki Kaya , Seiji Mochizuki , Ryoji Hashimoto
IPC: H04N5/232 , H04N19/124 , H04N19/20 , H04N19/159 , H04N19/176 , H04N19/172 , H04N19/13 , H04N19/149 , H04N19/15 , H04N19/115 , H04N19/60 , H04N19/61 , H04N19/132 , H04N19/14 , H04N19/137 , H04N19/142 , H04N19/152 , H04N19/182 , H04N19/184 , H04N19/85
Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
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4.发明授权公开(公告)号：US10362306B2
公开(公告)日：2019-07-23
申请号：US14830606
申请日：2015-08-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuya Shibayama , Seiji Mochizuki , Katsushige Matsubara , Kenichi Iwata
IPC: H04B1/66 , H04N19/124 , H04N19/117 , H04N19/103 , H04N19/46 , H04N19/115 , H04N19/136 , H04N19/54 , G06K9/46 , G06K9/62 , H04N19/61 , H04N19/154
Abstract: Included are an encoding section, a decoding section, and an image recognition section. The encoding section performs an encoding process for a video signal to be input based on a calculated encoding mode, and transmits an encoded stream. The decoding section performs a decoding process for the received encoded stream, and outputs a decoded image. The image recognition section performs an image recognition process for the decoded image. The encoding section adjusts the encoding mode based on recognition accuracy information representing the certainty of a recognition result in the image recognition section.
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公开(公告)号：US10225563B2
公开(公告)日：2019-03-05
申请号：US15206248
申请日：2016-07-09
Applicant: Renesas Electronics Corporation
Inventor： Tomohiro Une , Takahiko Sugimoto , Kwangsoo Park , Toshiyuki Kaya , Tetsuya Shibayama , Seiji Mochizuki
IPC: G06K9/00 , H04N19/186 , H04N19/117 , H04N19/80 , H04N19/36
Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
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Patent Agency Ranking
公开(公告)号：US20150092849A1
公开(公告)日：2015-04-02
申请号：US14505278
申请日：2014-10-02
Applicant: Renesas Electronics Corporation
Inventor： Tetsuya Shibayama , Seiji Mochizuki , Kenichi Iwata , Motoki Kimura
CPC classification number: H04N19/44 , H04N19/436 , H04N19/61
Abstract: Disclosed is a video decoding processing apparatus which can reduce overhead for the start of parallel decoding processing. The video decoding processing apparatus includes a parsing unit, and first and second video processing units. A coding bit stream including information of largest coding units each having at least a prescribed pixel size is supplied to an input terminal of the parsing unit. The parsing unit performs parsing of the syntax of the coding bit stream to thereby generate parallel-processable first and second intermediate streams from the largest coding unit. The first and second video processing units parallel-process the first and second intermediate streams generated from the parsing unit.
Abstract translation: 公开了一种可以减少并行解码处理开始的开销的视频解码处理装置。 视频解码处理装置包括解析单元和第一和第二视频处理单元。 包括至少具有规定像素大小的最大编码单位的信息的编码比特流被提供给解析单元的输入端。 解析单元执行对编码比特流的语法的解析，从而从最大编码单元生成可并行处理的第一和第二中间流。 第一和第二视频处理单元并行处理从解析单元生成的第一和第二中间流。
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公开(公告)号：US11726864B2
公开(公告)日：2023-08-15
申请号：US16821915
申请日：2020-03-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Katsushige Matsubara , Ryoji Hashimoto , Takahiro Irita , Kenichi Shimada , Tetsuya Shibayama
CPC classification number: G06F11/1004 , G06F9/30189 , G06F11/0772 , G06F11/108 , G06F11/3037
Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
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8.发明授权公开(公告)号：US11102475B2
公开(公告)日：2021-08-24
申请号：US16662182
申请日：2019-10-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Maiki Hosokawa , Toshiyuki Kaya , Tetsuya Shibayama , Seiji Mochizuki , Tomohiro Une , Kazushi Akie
IPC: H04N19/105 , H04N19/139 , H04N19/146 , H04N19/172 , H04N5/232
Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
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公开(公告)号：US10123022B2
公开(公告)日：2018-11-06
申请号：US14749505
申请日：2015-06-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Toshiyuki Kaya , Seiji Mochizuki , Tetsuya Shibayama , Kenichi Iwata , Hiroshi Ueda , Ren Imaoka
IPC: H04N19/12 , H04N19/159 , H04N19/176 , H04N19/433 , H04N19/436 , H04N19/597 , H04N19/105 , H04N19/16
Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.
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公开(公告)号：US09961346B2
公开(公告)日：2018-05-01
申请号：US14505369
申请日：2014-10-02
Applicant: Renesas Electronics Corporation
Inventor： Seiji Mochizuki , Tetsuya Shibayama
IPC: H04N19/126 , H04N19/593 , H04N19/176 , H04N19/149 , H04N19/115 , H04N19/124 , H04N19/146 , H04N19/152 , H04N19/50
CPC classification number: H04N19/126 , H04N19/115 , H04N19/124 , H04N19/146 , H04N19/149 , H04N19/152 , H04N19/176 , H04N19/50 , H04N19/593
Abstract: The present invention provides a video encoder and a method of operating the video encoder to implement high-precision bit rate control by reducing the risk of overflow of an intermediate buffer coupled between a quantizer and an encoding section. The intermediate buffer supplies a selection control signal indicative of whether the amount of stored data is large or small to a selector. If the selection control signal indicates large, the selector outputs an estimated code amount from a code amount estimation section to the rate controller. If the selection control signal indicates small, the selector outputs an actual code amount from the encoding section to the rate controller. The rate controller calculates the quantization scale according to the output of the selector and feedbacks the calculated quantization scale to the quantizer. The quantizer adjusts the quantizer scale.
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