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公开(公告)号：US11360529B2
公开(公告)日：2022-06-14
申请号：US16842399
申请日：2020-04-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroshi Ueda , Ryoji Hashimoto , Taku Maekawa , Katsushige Matsubara , Keisuke Matsumoto
Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
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公开(公告)号：US10241706B2
公开(公告)日：2019-03-26
申请号：US15582252
申请日：2017-04-28
Applicant: Renesas Electronics Corporation
Inventor： Seiji Mochizuki , Katsushige Matsubara , Ren Imaoka , Hiroshi Ueda , Ryoji Hashimoto , Toshiyuki Kaya
Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
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公开(公告)号：US09877044B2
公开(公告)日：2018-01-23
申请号：US15618316
申请日：2017-06-09
Applicant: Renesas Electronics Corporation
Inventor： Kenichi Iwata , Seiji Mochizuki , Toshiyuki Kaya , Ryoji Hashimoto
IPC: H04B1/66 , H04N19/513 , H04N19/105 , H04N19/174 , H04N19/167 , H04N19/55 , H04N19/51 , H04N19/436 , H04N19/86
CPC classification number: H04N19/521 , H04N19/105 , H04N19/167 , H04N19/174 , H04N19/436 , H04N19/51 , H04N19/55 , H04N19/86
Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
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4.发明授权公开(公告)号：US09800874B2
公开(公告)日：2017-10-24
申请号：US14304943
申请日：2014-06-15
Applicant: Renesas Electronics Corporation
Inventor： Ryoji Hashimoto , Toshiyuki Kaya
IPC: H04N19/167 , H04N19/176 , H04N19/152 , H04N19/117 , H04N19/174 , H04N19/44 , H04N19/467 , H04N19/80 , H04N19/33 , H04N19/423
CPC classification number: H04N19/174 , H04N19/117 , H04N19/152 , H04N19/167 , H04N19/176 , H04N19/33 , H04N19/423 , H04N19/44 , H04N19/467 , H04N19/80
Abstract: For a decoding apparatus based on H.265/HEVC with single-core or single-threaded hardware not parallelized, which executes decoding a plurality of tiles and filtering around a tile boundary, the disclosed invention is intended to reduce the frequency of access to decoded data around the boundaries between tiles stored in a frame memory for filtering such data or reduce the circuit size of a buffer that retains decoded data around the boundaries between tiles. The image decoding apparatus disclosed herein executes decoding and filtering in raster scan order across a screen independently of the sizes and positional relations of tiles. At a tile boundary, decoding proceeds to a right adjacent tile on the same row, rather than decoding coding blocks on one row down in the same tile, and filtering is also executed using decoded data of row-wise adjacent coding blocks.
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公开(公告)号：US09712842B2
公开(公告)日：2017-07-18
申请号：US15149648
申请日：2016-05-09
Applicant: Renesas Electronics Corporation
Inventor： Kenichi Iwata , Seiji Mochizuki , Toshiyuki Kaya , Ryoji Hashimoto
IPC: H04B1/66 , H04N19/513 , H04N19/105 , H04N19/174 , H04N19/167 , H04N19/436 , H04N19/55 , H04N19/51 , H04N19/86
CPC classification number: H04N19/521 , H04N19/105 , H04N19/167 , H04N19/174 , H04N19/436 , H04N19/51 , H04N19/55 , H04N19/86
Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
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Patent Agency Ranking
公开(公告)号：US10725512B2
公开(公告)日：2020-07-28
申请号：US15858361
申请日：2017-12-29
Applicant: Renesas Electronics Corporation
Inventor： Hiroshi Ueda , Ryoji Hashimoto , Taku Maekawa , Katsushige Matsubara , Keisuke Matsumoto
Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
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公开(公告)号：US09832483B2
公开(公告)日：2017-11-28
申请号：US15618316
申请日：2017-06-09
Applicant: Renesas Electronics Corporation
Inventor： Kenichi Iwata , Seiji Mochizuki , Toshiyuki Kaya , Ryoji Hashimoto
IPC: H04B1/66 , H04N19/513 , H04N19/105 , H04N19/174 , H04N19/167 , H04N19/55 , H04N19/51 , H04N19/436 , H04N19/86
Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
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公开(公告)号：US20150003513A1
公开(公告)日：2015-01-01
申请号：US14304943
申请日：2014-06-15
Applicant: Renesas Electronics Corporation
Inventor： Ryoji Hashimoto , Toshiyuki Kaya
IPC: H04N19/167 , H04N19/176 , H04N19/152 , H04N19/117
CPC classification number: H04N19/174 , H04N19/117 , H04N19/152 , H04N19/167 , H04N19/176 , H04N19/33 , H04N19/423 , H04N19/44 , H04N19/467 , H04N19/80
Abstract: For a decoding apparatus based on H.265/HEVC with single-core or single-threaded hardware not parallelized, which executes decoding a plurality of tiles and filtering around a tile boundary, the disclosed invention is intended to reduce the frequency of access to decoded data around the boundaries between tiles stored in a frame memory for filtering such data or reduce the circuit size of a buffer that retains decoded data around the boundaries between tiles. The image decoding apparatus disclosed herein executes decoding and filtering in raster scan order across a screen independently of the sizes and positional relations of tiles. At a tile boundary, decoding proceeds to a right adjacent tile on the same row, rather than decoding coding blocks on one row down in the same tile, and filtering is also executed using decoded data of row-wise adjacent coding blocks.
Abstract translation: 对于基于不并行化的单核或单线程硬件的H.265 / HEVC的解码装置，其执行对多个瓦片进行解码并围绕瓦片边界进行滤波，所公开的发明旨在降低对解码的访问频率 围绕存储在帧存储器中的块之间的边界周围的数据，用于对这些数据进行滤波或者减小保留解码的数据在块之间的边界周围的缓冲器的电路大小。 本文公开的图像解码装置独立于瓦片的尺寸和位置关系执行扫描顺序的光栅扫描顺序的解码和滤波。 在瓦片边界处，解码进行到相同行上的右邻近瓦片，而不是在同一瓦片中的一行下行解码编码块，并且还使用逐行相邻编码块的解码数据执行滤波。
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公开(公告)号：US11726864B2
公开(公告)日：2023-08-15
申请号：US16821915
申请日：2020-03-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Katsushige Matsubara , Ryoji Hashimoto , Takahiro Irita , Kenichi Shimada , Tetsuya Shibayama
CPC classification number: G06F11/1004 , G06F9/30189 , G06F11/0772 , G06F11/108 , G06F11/3037
Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
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10.发明授权公开(公告)号：US10977834B2
公开(公告)日：2021-04-13
申请号：US16409502
申请日：2019-05-10
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Ryoji Hashimoto , Keisuke Matsumoto , Nhat Van Huynh
IPC: G06T9/00 , G06T1/60 , H04N19/423 , H04N19/80 , H04N19/85 , H04N19/42 , H04N19/176 , H04N19/86 , H04N19/625
Abstract: The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit.
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