公开(公告)号：US11868277B2

公开(公告)日：2024-01-09

申请号：US17559113

申请日：2021-12-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Sugita

IPC: G06F12/14 ,  G06F12/0866

CPC classification number: G06F12/145 ,  G06F12/0866 ,  G06F12/1458 ,  G06F2212/152

Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.

公开(公告)号：US11188373B2

公开(公告)日：2021-11-30

申请号：US16404162

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Sugita

IPC: G06F9/455 ,  G06F7/48 ,  G06F9/48 ,  G06F9/30

Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.

公开(公告)号：US10706178B2

公开(公告)日：2020-07-07

申请号：US15808960

申请日：2017-11-10

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Sugita ,  Koji Adachi ,  Yoichi Yuyama

IPC: G06F7/04 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G11C7/00 ,  G06F21/70 ,  G06F21/62

Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.

公开(公告)号：US09535845B2

公开(公告)日：2017-01-03

申请号：US14052616

申请日：2013-10-11

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Sugita

IPC: G06F12/12 ,  G06F12/08 ,  G06F9/50

CPC classification number: G06F12/0871 ,  G06F9/5016 ,  G06F12/08 ,  G06F12/12 ,  G06F12/122

Abstract: A cache control device includes an area determination unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of an allocation ratio of an execution time per unit time, which is allocated to each of a plurality of the instruction flows by a CPU. The area determination unit specifies the area allocated to the specified instruction flow in response to an access request from a memory access unit, and accesses the specified area in the cache memory.

Abstract translation: 高速缓存控制装置包括区域确定单元，其基于分配给多个指令中的每一个的每单位时间的执行时间的分配比，确定分配给每个指令流的高速缓冲存储器的区域 由CPU流动。 区域确定单元响应于来自存储器访问单元的访问请求指定分配给指定指令流的区域，并访问高速缓冲存储器中的指定区域。

公开(公告)号：US11915032B2

公开(公告)日：2024-02-27

申请号：US17509768

申请日：2021-10-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Sugita

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/30 ,  G06F7/48

CPC classification number: G06F9/45558 ,  G06F9/3001 ,  G06F9/4812 ,  G06F7/48

Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.

公开(公告)号：US11237987B2

公开(公告)日：2022-02-01

申请号：US16411492

申请日：2019-05-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Sugita

IPC: G06F12/14 ,  G06F12/0866

Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.

公开(公告)号：US10936357B2

公开(公告)日：2021-03-02

申请号：US16189449

申请日：2018-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro Sugita

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/30 ,  G06F9/54

Abstract: There is a need to provide a semiconductor device that improves an interrupt capability of a virtual machine. A semiconductor device includes a memory to store a plurality of virtual machines and a virtual machine manager to manage the virtual machines and a CPU to perform the virtual machines and the virtual machine manager. The CPU causes an active virtual machine to perform an interrupt process when information (first information) about an interrupt-processing virtual machine is equal to information (second information) about the active virtual machine. When the first information differs from the second information, the CPU causes the virtual machine manager to stop the active virtual machine and operates the interrupt-processing virtual machine to perform an interrupt process.