公开(公告)号：US10291238B2

公开(公告)日：2019-05-14

申请号：US15441936

申请日：2017-02-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Atsushi Motozawa ,  Yoshitaka Hirai

IPC分类号： H03L7/06 ,  H03L7/08 ,  H03L7/099 ,  H03L7/087 ,  H03K19/0175 ,  H02M3/07 ,  H03L7/18 ,  H03M1/74

摘要： An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

公开(公告)号：US09553718B2

公开(公告)日：2017-01-24

申请号：US14960952

申请日：2015-12-07

申请人： Renesas Electronics Corporation

发明人： Yoshitaka Hirai

IPC分类号： H03D3/24 ,  H04L7/033

CPC分类号： H04L7/0331 ,  H03L7/0893 ,  H04L7/033

摘要： According to one embodiment, a PLL circuit includes: a phase comparator (13); a pulse width control unit that adjusts a pulse width of comparison results (UP, DN) of the phase comparator (13) and outputs comparison results (UPi, DNi) having a pulse width smaller than that of comparison results (UPp, DNp); a charge pump (14) that outputs a current (Ip) according to the comparison results (UPp, DNp); a charge pump (15) that outputs a current (Ii) according to the comparison results (UPi, DNi); a filter (16) that removes a high-frequency component of a voltage generated based on the current (Ip) and outputs a control voltage (Vp); a filter (17) that outputs, as a control voltage (Vi), a result obtained by integrating the current (Ii); and a voltage control oscillator (18) that generates an oscillating signal having a frequency according to the control voltage (Vp, Vi).

摘要翻译： 根据一个实施例，PLL电路包括：相位比较器（13）; 脉冲宽度控制单元，调整相位比较器（13）的比较结果（UP，DN）的脉冲宽度，并输出脉冲宽度小于比较结果（UPp，DNp）的比较结果（UPi，DNi）。 根据比较结果（UPp，DNp）输出电流（Ip）的电荷泵（14）; 根据比较结果（UPi，DNi）输出电流（Ii）的电荷泵（15）; 滤波器（16），其去除基于所述电流（Ip）产生的电压的高频分量并输出控制电压（Vp）; 输出作为控制电压（Vi）的电流（Ii）积分的滤波器（17）; 以及电压控制振荡器（18），其产生具有根据所述控制电压（Vp，Vi）的频率的振荡信号。