公开(公告)号：US11128281B2

公开(公告)日：2021-09-21

申请号：US16569060

申请日：2019-09-12

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G05F1/04 ,  H03K3/012 ,  G06F1/06 ,  G06F1/10 ,  H03K3/356 ,  H03K17/687

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

公开(公告)号：US11023631B2

公开(公告)日：2021-06-01

申请号：US16024613

申请日：2018-06-29

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F30/00 ,  G06F30/327 ,  H03K19/096 ,  H03K19/00 ,  G06F30/36 ,  G06F30/35 ,  G06F119/06

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US11763055B2

公开(公告)日：2023-09-19

申请号：US17317500

申请日：2021-05-11

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F30/00 ,  G06F30/35 ,  H03K19/096 ,  H03K19/00 ,  G06F30/36 ,  G06F30/327 ,  G06F119/06 ,  H03K5/15 ,  H02M7/48

CPC classification number: G06F30/35 ,  G06F30/327 ,  G06F30/36 ,  H03K19/0019 ,  H03K19/0963 ,  H03K19/0966 ,  G06F2119/06 ,  H02M7/4826 ,  H02P2201/05 ,  H03K5/15

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US10454455B2

公开(公告)日：2019-10-22

申请号：US15974226

申请日：2018-05-08

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F1/04 ,  H03K3/00 ,  H03K3/012 ,  G06F1/06 ,  G06F1/10 ,  H03K3/356 ,  H03K17/687

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

公开(公告)号：US12153867B2

公开(公告)日：2024-11-26

申请号：US18204230

申请日：2023-05-31

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F30/373 ,  G06F30/327 ,  G06F30/35 ,  G06F30/36 ,  G06F119/06 ,  H02M7/48 ,  H03K5/15 ,  H03K19/00 ,  H03K19/096

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US20230306174A1

公开(公告)日：2023-09-28

申请号：US18204230

申请日：2023-05-31

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F30/35 ,  H03K19/096 ,  H03K19/00 ,  G06F30/36 ,  G06F30/327

CPC classification number: G06F30/35 ,  H03K19/0963 ,  H03K19/0019 ,  H03K19/0966 ,  G06F30/36 ,  G06F30/327 ,  G06F2119/06

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US10340895B2

公开(公告)日：2019-07-02

申请号：US15974240

申请日：2018-05-08

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: H03K17/687 ,  H03K3/012 ,  G06F1/06 ,  G06F1/10 ,  H03K3/356

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.