公开(公告)号：US20210375889A1

公开(公告)日：2021-12-02

申请号：US17330381

申请日：2021-05-25

申请人： ROHM CO., LTD.

发明人： Yushi SEKIGUCHI ,  Yasunobu HAYASHI ,  Tadayuki YAMAZAKI

IPC分类号： H01L27/112

摘要： A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.

公开(公告)号：US20240355892A1

公开(公告)日：2024-10-24

申请号：US18763081

申请日：2024-07-03

申请人： ROHM CO., LTD.

发明人： Yasunobu HAYASHI

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51

CPC分类号： H01L29/4234 ,  H01L29/408 ,  H01L29/51 ,  H01L29/40117

摘要： A semiconductor device includes a planar gate structure including a gate insulating film and a gate electrode, and a sidewall structure disposed adjacent to a lateral side of the planar gate structure. The sidewall structure includes a first insulating film and a second insulating film, and a charge storage film disposed between the first insulating film and the second insulating film. The first insulating film is adjacent to the planar gate structure. A ratio between a gate length L of the planar gate structure and a width WS of the sidewall structure is less than or equal to 300/75. Thereby, a semiconductor device having an improved data read and write reliability in a memory structure can be provided.

公开(公告)号：US20230085550A1

公开(公告)日：2023-03-16

申请号：US17899057

申请日：2022-08-30

申请人： ROHM CO., LTD.

发明人： Yasunobu HAYASHI

IPC分类号： H01L29/792 ,  H01L29/78

摘要： A semiconductor device includes: a semiconductor layer having a main surface; a first-conduction-type well region formed on a surface portion of the main surface of the semiconductor layer; a second-conduction-type first region formed on a surface portion of the well region; a second-conduction-type second region formed on the surface portion of the well region at an interval from the first region; a first-conduction-type diffusion layer formed on the surface portion of the main surface adjacent to the first region; a planar gate structure formed on the main surface of the semiconductor layer to face a first-conduction-type channel region between the first region and the second region; and a memory structure including a charge storage film arranged adjacent to a lateral side of the planar gate structure on a side of the first region.

公开(公告)号：US20220376051A1

公开(公告)日：2022-11-24

申请号：US17775524

申请日：2020-11-30

申请人： ROHM CO., LTD.

发明人： Yasunobu HAYASHI

IPC分类号： H01L29/10 ,  H01L21/74

摘要： A semiconductor device includes a semiconductor layer, a source region and a drain region that are formed in the semiconductor layer and at an interval in a first direction, a gate insulating film that is formed such as to cover a channel region between the source region and the drain region, and a gate electrode that is formed on the gate insulating film and opposes the channel region across the gate insulating film. The gate insulating film has a major portion on which the gate electrode is formed and extension portions projecting outward from each of both sides of the major portion in a second direction orthogonal to the first direction and leak current suppressing electrodes are formed on the extension portions.

公开(公告)号：US20220130844A1

公开(公告)日：2022-04-28

申请号：US17569981

申请日：2022-01-06

申请人： ROHM CO., LTD.

发明人： Tadayuki YAMAZAKI ,  Yasunobu HAYASHI ,  Goro SHIMIZU

IPC分类号： H01L27/112

摘要： A memory cell formed on the surface of a p-well of a semiconductor substrate includes a drain region and a source region that are formed with a channel region therebetween; an insulating film that is formed to cover the channel region; a gate that is formed on the insulating film; sidewall spacers that are formed to be positioned at side surfaces of the gate and directly above the channel region; a salicide block film that is formed to cover a portion of the drain region, a portion of the source regio, the gat, and the sidewall spacers; a drain salicide layer and a source salicide layer that are formed at the salicide block film and on the drain region and the source region exposed from the salicide block film; and a nitride film that is formed to cover the salicide block film, the drain salicide layer, and the source salicide layer.