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1.发明授权公开(公告)号：US06714197B1
公开(公告)日：2004-03-30
申请号：US09364787
申请日：1999-07-30
IPC分类号： G06T1520
CPC分类号： G06T15/00 , G06F9/30014 , G06F9/30025 , G06F9/345 , G06T15/20
摘要： A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.
摘要翻译： 具有包含一组高性能浮点运算的指令集架构的算术扩展的处理器。 指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。 该扩展包括针对减少添加，减少乘数，倒数和倒数平方根的指令。
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2.发明授权公开(公告)号：US06490642B1
公开(公告)日：2002-12-03
申请号：US09373092
申请日：1999-08-12
申请人： Radhika Thekkath , G. Michael Uhler
发明人： Radhika Thekkath , G. Michael Uhler
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.
摘要翻译： 提出了一种用于提高通过片上系统总线互连的设备之间的数据传输的效率的装置，其中多主计算机系统配置。 通过提供一种用于控制在业务中不暂停系统总线的基本特征（即，流水线和事务分割）的总线从设备中的地址的读 - 修改 - 写事务的装置。 该装置包括总线主设备中的事务控制逻辑和总线从设备中的事务响应逻辑。 交易控制逻辑通过片上系统总线向总线从设备提供来自总线主设备的写屏障命令。 交易响应逻辑接收写入障碍命令，并且排除对总线从设备中的地址的未来事务的执行，直到完成读 - 修改 - 写入事务，同时允许对总线从设备中的其他地址执行事务来完成。
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公开(公告)号：US07724261B2
公开(公告)日：2010-05-25
申请号：US11806845
申请日：2007-06-04
IPC分类号： G06T1/20
CPC分类号： G06T15/005 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/3885
摘要： A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
摘要翻译： 具有包含一组高性能浮点运算的指令集架构的比较扩展的处理器。 指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。 该扩展包括针对浮点数的幅度比较和一对32位固定点整数与配对单个浮点格式之间的转换的指令。
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公开(公告)号：US06493776B1
公开(公告)日：2002-12-10
申请号：US09373091
申请日：1999-08-12
IPC分类号： G06F946
CPC分类号： G06F13/4217
摘要： An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.
摘要翻译： 提供具有单独的地址和数据部分的片上分离事务系统总线。 系统总线包含单独的地址和数据总线，用于在总线的地址或数据部分的一个或两个上启动和跟踪无序事务。 系统总线通过总线接口提供通信，该总线接口包括拆分事务跟踪和控制，以为由总线接口发起的每个事务建立事务ID，并确定出现在系统总线的数据部分上的数据是否与其未决的其中一个相关联 交易。 总线接口还包含流控制逻辑，以确定要由总线接口读取或写入的器件是否具有可用于响应事务的资源（缓冲器）。 如果资源可用，流控制逻辑允许事务进行，并调整其计数器以反映资源的使用。 如果资源不可用，则流控制逻辑导致事务等待直到资源变得可用。
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公开(公告)号：US07065675B1
公开(公告)日：2006-06-20
申请号：US09850195
申请日：2001-05-08
IPC分类号： G06F11/00
CPC分类号： G01R31/318544 , G01R31/31705
摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.
摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。
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6.发明授权Processor having a conditional branch extension of an instruction set architecture 有权具有指令集架构的条件分支扩展的处理器公开(公告)号：US06732259B1
公开(公告)日：2004-05-04
申请号：US09364789
申请日：1999-07-30
IPC分类号： G06F930
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/3885
摘要： A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.
摘要翻译： 具有包含一组高性能浮点运算的指令集架构的条件分支扩展的处理器。 指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。 如果两个条件代码中的任一个为假或真，如果三个条件代码中的任何一个为假或真，或者四个条件代码中的任何一个为假或真，则扩展包括指向分支的指令。
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公开(公告)号：US06681283B1
公开(公告)日：2004-01-20
申请号：US09373094
申请日：1999-08-12
申请人： Radhika Thekkath , G. Michael Uhler
发明人： Radhika Thekkath , G. Michael Uhler
IPC分类号： G06F1300
CPC分类号： G06F12/0815
摘要： A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transactions, and a cache for storing coherent data. The coherency credit counter tracks coherent transactions pending in a memory controller, and delays coherent transactions from being placed on the bus if coherent resources are not available in the memory controller. When resources become available in the memory controller, the memory controller signals the coherency system in each of the master devices. The coherency system is coupled to a split transaction tracking and control to establish transaction ID's for each coherent transaction initiated by its master device, and presents a transaction ID along with an address portion of each coherent transaction.
摘要翻译： 提供了用于片上计算总线的高速缓存一致性系统。 一致性系统在片上总线上的每个主设备中包含一个相干性信用计数器，用于监视总线上可用于相干事务的资源，用于存储相干事务的一致性输入缓冲器以及用于存储相干数据的高速缓存。 相干信用计数器跟踪存储器控制器中等待的相干事务，并且如果在存储器控制器中不可用相干资源，则将相干事务延迟放置在总线上。 当存储器控制器中的资源变得可用时，存储器控制器向每个主设备中的相关系统发信号。 相关系统耦合到分割事务跟踪和控制，以为由其主设备发起的每个相干事务建立事务ID，并且将交易ID与每个相干事务的地址部分一起呈现。
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公开(公告)号：US07242414B1
公开(公告)日：2007-07-10
申请号：US09364786
申请日：1999-07-30
IPC分类号： G09G5/30
CPC分类号： G06T15/005 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/3885
摘要： A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
摘要翻译： 具有包含一组高性能浮点运算的指令集架构的比较扩展的处理器。 指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。 该扩展包括针对浮点数的幅度比较和一对32位固定点整数与配对单个浮点格式之间的转换的指令。
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公开(公告)号：US06604159B1
公开(公告)日：2003-08-05
申请号：US09373093
申请日：1999-08-12
申请人： Radhika Thekkath , G. Michael Uhler
发明人： Radhika Thekkath , G. Michael Uhler
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains a data release mechanism to reduce turn around time of the data bus between competing data bus masters. The data release mechanism is incorporated within the bus interface of all data bus masters. A data bus master drives data release during the last cycle of a data transaction. Another data bus masters (awaiting mastership) receives the data release and begin driving the data bus one cycle after seeing data release.
摘要翻译： 提供具有单独的地址和数据部分的片上分离事务系统总线。 系统总线包含单独的地址和数据总线，用于在总线的地址或数据部分的一个或两个上启动和跟踪事务。 系统总线通过总线接口提供通信，该总线接口包括拆分事务跟踪和控制，以为由总线接口发起的每个事务建立事务ID，并确定出现在系统总线的数据部分上的数据是否与其未决的其中一个相关联 交易。 总线接口还包含数据发布机制，以减少竞争数据总线主机之间的数据总线的周转时间。 数据发布机制并入所有数据总线主站的总线接口。 数据总线主机在数据事务的最后一个周期中驱动数据释放。 数据总线主机（等待掌握）接收数据发布，并在看到数据发布后一周期开始驱动数据总线。
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公开(公告)号：US08185879B2
公开(公告)日：2012-05-22
申请号：US11557005
申请日：2006-11-06
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.
摘要翻译： 用于跟踪多任务嵌入式流水线处理器的方法包括执行包括跟踪控制的编译代码。 执行编译代码时启动跟踪。 编译代码的执行完成后，跟踪停止。 在跟踪期间形成跟踪记录。 跟踪记录包括处理器模式指示，应用空间标识值和指令体系结构设置模式指示。
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