公开(公告)号：US5717885A

公开(公告)日：1998-02-10

申请号：US741749

申请日：1996-11-05

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a lower portion. The upper portion is always compared to an upper virtual page number entry in a first content addressable memory while only certain bits of lower portion are selectively compared to a corresponding number of bits in a lower virtual page number entry in a second content addressable memory. The number of bits compared in the second content addressable memory is determined by the specified size of the physical page. The TLB includes a page size memory having a plurality of page size entries wherein the certain number of bits for each of the lower virtual page entries is specified by a corresponding page size entry. Associated with each bit in the lower virtual page number entries is an enable transistor for selectively enabling the comparison of that bit in the lower virtual page number entry. The enable gate includes a control input coupled to a corresponding bit in a corresponding page size entry, the enable transistor selectively enabling the single bit comparison when the corresponding bit in the page size entry is set to an enable state and selectively disabling the comparison when the corresponding bit in the page size entry is set to a disable state.

摘要翻译： 用于将可变页大小的虚拟页号翻译成物理页号的翻译后备缓冲器（TLB）。 TLB将虚拟页码分成上部和下部。 上部部分总是与第一内容可寻址存储器中的上虚拟页号码条目进行比较，而仅将下部分的某些比特选择性地与第二内容可寻址存储器中的较低虚拟页号码条目中的相应位数比较。 在第二内容可寻址存储器中比较的比特数由物理页面的指定大小确定。 TLB包括具有多个页面大小条目的页面大小存储器，其中每个较低虚拟页面条目的特定数量的位由相应的页面大小条目指定。 与较低虚拟页号码条目中的每个位相关联的是使能晶体管，用于选择性地启用较低虚拟页码条目中该位的比较。 使能栅极包括耦合到相应页面大小条目中的对应位的控制输入，当页面大小条目中的相应位被设置为使能状态时，使能晶体管有选择地启用单个位比较，并且当 页面大小条目中的相应位被设置为禁用状态。

公开(公告)号：US5649154A

公开(公告)日：1997-07-15

申请号：US547047

申请日：1995-10-23

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0862

摘要： A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output data bitlines, sense amplifiers, and bus drivers as the direct mapped cache. In a first machine cycle, input address tags are simultaneously compared to tag bits in the primary cache and the secondary cache. If the comparison results in a miss in the primary cache and a hit in the secondary cache, the secondary cache data is fed to the microprocessor in the next machine cycle, precluding the need for a main memory access. Thus, allowing data to be read directly from the secondary cache without using an extra machine cycle to load it first into the direct cache. The secondary cache comprises a miss cache which is loaded from main memory with data missing from the primary cache in the first machine cycle. Alternatively, the secondary cache comprises a victim cache which is loaded with a line of the primary cache which is replaced after loading missed data from main memory.

摘要翻译： 一种高速缓冲存储器系统，其具有与直接映射的一级高速缓存集成的二级缓存，其中单个结构优选地构造在VLSI芯片上。 二级缓存使用相同的输出数据位线，读出放大器和总线驱动器作为直接映射缓存。 在第一个机器周期中，输入地址标签与主缓存和二级缓存中的标签位同时进行比较。 如果比较导致主缓存中的未命中和次级高速缓存中的命中，则次级高速缓存数据在下一个机器周期中被馈送到微处理器，排除了对主存储器访问的需要。 因此，允许直接从二级缓存读取数据，而不用额外的机器周期将其首先加载到直接高速缓存中。 次级高速缓存包括从主存储器加载的未命中高速缓存，其中在第一机器周期中从主缓存中缺少数据。 或者，辅助高速缓存包括被加载有主缓存的行的受害缓存，在从主存储器加载丢失的数据之后被替换。

公开(公告)号：US5513363A

公开(公告)日：1996-04-30

申请号：US293862

申请日：1994-08-22

申请人： Rajendra Kumar ,  Paul G. Emerson

发明人： Rajendra Kumar ,  Paul G. Emerson

IPC分类号： G06F9/30 ,  G06F9/38 ,  G11C8/16 ,  G06F9/00

CPC分类号： G06F9/30141 ,  G06F9/3012 ,  G06F9/3875 ,  G11C8/16

摘要： A scalable register file including first and second micro-register files organized in a pipelined fashion to minimize the access time of the register file where there are a large number of registers or multiple functional units. Interposed between the first and second micro-register files are a first plurality of pipeline registers for storing the register contents fetched from the first micro-register file during a first pipeline cycle. A second plurality of pipeline registers are coupled to the second micro-register files for storing the register contents fetched from the second micro-register file during a second pipeline stage and those registers being stored in the first plurality of pipeline registers. The first plurality of pipeline registers are coupled to the bit lines of the second micro-register file. Enable logic is coupled to each of the first plurality pipeline registers to selectively present the contents of the first plurality of pipeline register to the second plurality of pipeline registers if there were contents stored in a first pipeline register during the first pipeline cycle. Alternatively, a multiplexer can be used to present the register contents stored in the first plurality of pipeline registers to the second plurality of pipeline registers.

摘要翻译： 一种可扩展的寄存器文件，包括以流水线方式组织的第一和第二微寄存器文件，以最小化寄存器文件的存储时间，其中存在大量寄存器或多个功能单元。 介于第一和第二微寄存器文件之间的是第一多个流水线寄存器，用于存储在第一流水线循环期间从第一微寄存器文件获取的寄存器内容。 第二多个流水线寄存器耦合到第二微寄存器文件，用于存储在第二流水线级期间从第二微寄存器文件获取的寄存器内容，并且这些寄存器被存储在第一多个流水线寄存器中。 第一组多个流水线寄存器耦合到第二微寄存器堆的位线。 如果在第一流水线循环期间存在第一流水线寄存器中的内容，则启用逻辑被耦合到第一多个流水线寄存器中的每一个，以便有选择地将第一多个流水线寄存器的内容呈现给第二多个流水线寄存器。 或者，可以使用多路复用器将存储在第一多个流水线寄存器中的寄存器内容呈现给第二多个流水线寄存器。

公开(公告)号：US09071494B2

公开(公告)日：2015-06-30

申请号：US13486608

申请日：2012-06-01

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04L27/00 ,  H04L27/26 ,  H04L27/20 ,  H03H21/00

CPC分类号： H04L27/2657 ,  H03H21/003 ,  H04L27/20 ,  H04L27/2676 ,  H04L27/2688

摘要： Systems and methods are provided for fast and precise estimation of frequency with relatively minimal sampling and relatively high tolerance to noise.

公开(公告)号：US08995542B2

公开(公告)日：2015-03-31

申请号：US13913761

申请日：2013-06-10

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04K1/10 ,  H04L27/28 ,  H04L27/26

CPC分类号： H04L27/2602 ,  H04L27/2614 ,  H04L27/2615 ,  H04L27/2618

摘要： Various embodiments of the invention are directed to methods and systems for multi transform OFDM transmitter and receivers with low peak to average power ratio (PAPR) signals, that have high bandwidth efficiency and are computational efficient. For example, various embodiments of the transmitter may utilize an architecture comprised of a baseband modulator, a serial to parallel converter, a bank of multiplicity NT orthonormal transforms unit, a bank of multiplicity NT inverse Fourier transforms unit, a dummy symbols generator, and a minimum PAPR evaluation unit for finding the optimum transform index n0. Various embodiments of the receiver may comprise of a transform index detection unit for the detection of the transform index imbedded in the OFDM signal.

摘要翻译： 本发明的各种实施例涉及具有低峰值与平均功率比（PAPR）信号的具有高带宽效率并且具有计算效率的多变换OFDM发射机和接收机的方法和系统。 例如，发射机的各种实施例可以利用包括基带调制器，串行到并行转换器，多重组NT正交变换单元组，多重组NT逆傅里叶变换单元组，虚拟符号发生器和 用于找到最佳变换索引n0的最小PAPR评估单元。 接收机的各种实施例可以包括用于检测嵌入在OFDM信号中的变换索引的变换索引检测单元。

公开(公告)号：US08982924B2

公开(公告)日：2015-03-17

申请号：US12660615

申请日：2010-03-02

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04B1/00 ,  G06F7/00 ,  H04L27/00 ,  H04L27/20

CPC分类号： G06F7/00 ,  H04L27/00 ,  H04L27/20

摘要： Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of −1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

摘要翻译： 各种实施例涉及用于组合多个代码的系统和方法。 多个代码可以是具有可能的逻辑值为-1和+1的二进制代码，并且可以包括偶数个代码。 组合v0，k的输出可以由下式给出：v0 = sgn（vi），其中vi是第一时间的第一个多个代码的和。 呈现了各种代码中分配不同功率电平的实施例。

公开(公告)号：US08711919B2

公开(公告)日：2014-04-29

申请号：US13434498

申请日：2012-03-29

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。

公开(公告)号：US08638890B2

公开(公告)日：2014-01-28

申请号：US13465606

申请日：2012-05-07

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H03D1/04

CPC分类号： H04L27/12 ,  H04L27/156

摘要： A receiver may comprise a complex mixer for converting the modulated signal to a complex modulated signal comprising a first in-phase component and a first quadrature component. The receiver may further comprise a digital demodulator. The digital demodulator may comprise at least one processor circuit programmed for applying a phase differencer for generating an output function in terms of a phase difference of the complex modulated signal. Applying the phase differencer may comprise converting the first in-phase component to a function of a phase difference of the first in-phase component expressed in digital time, and converting the first quadrature component to a function of the phase difference of the first quadrature component expressed in digital time. The at least one processor circuit of the digital demodulator may also be programmed for applying a four quadrant inverse tangent to the output function to generate the information signal.

摘要翻译： 接收机可以包括用于将调制信号转换成包括第一同相分量和第一正交分量的复调制信号的复合混频器。 接收机还可以包括数字解调器。 数字解调器可以包括至少一个处理器电路，其被编程用于施加相位差分器，用于根据复调制信号的相位差产生输出函数。 应用相位差分器可以包括将第一同相分量转换为以数字时间表示的第一同相分量的相位差的函数，并将第一正交分量转换为第一正交分量的相位差的函数 以数字时代表达。 数字解调器的至少一个处理器电路也可以被编程为向输出功能施加四象限反正切以产生信息信号。

公开(公告)号：US08612651B2

公开(公告)日：2013-12-17

申请号：US12599062

申请日：2008-05-14

申请人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

发明人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

IPC分类号： G06F3/00 ,  G06G5/00

CPC分类号： G06F5/12

摘要： A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

摘要翻译： FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针之后 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。

公开(公告)号：US20130259113A1

公开(公告)日：2013-10-03

申请号：US13434498

申请日：2012-03-29

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04L27/01 ,  H04B1/16

CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。