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29 条记录 (耗时 0.016 秒)

    Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores
    3.
    发明授权
    Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores 失效
    预测发出的无声存储操作，允许随后发出的负载绕过未执行的无声存储，并在执行存储时确认旁路

    公开(公告)号：US07062638B2

    公开(公告)日：2006-06-13

    申请号：US09752796

    申请日：2000-12-29

    申请人： Adi Yoaz ,  Ronny Ronen ,  Rajesh Patel

    发明人： Adi Yoaz ,  Ronny Ronen ,  Rajesh Patel

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3834 ,  G06F9/3832 ,  G06F9/3838

    摘要： An electronic device including a predictor that has a collision history table (CHT) is presented. An extended load buffer is connected to the predictor. Also included is a marking unit, a comparing unit and a recovery unit connected to the extended load buffer. Unexecuted load instructions are advanced over store instructions. Also presented is a method for fetching an instruction and determining if an instruction is a store or a load. If the instruction is a store, then the method performs a silent store prediction. If the instruction is a load, a predicted silent store instruction is bypassed and the load instruction is executed.

    摘要翻译： 提出了一种包括具有冲突历史表（CHT）的预测器的电子设备。 扩展加载缓冲区连接到预测器。 还包括标记单元，比较单元和连接到扩展加载缓冲器的恢复单元。 未执行的加载指令超过存储指令。 还提出了一种用于获取指令并确定指令是存储还是加载的方法。 如果指令是存储，则该方法执行静默存储预测。 如果指令是负载，则旁路预测的无声存储指令，并执行加载指令。

    Method and apparatus for predicting when load instructions can be executed out-of order
    5.
    发明授权
    Method and apparatus for predicting when load instructions can be executed out-of order 失效
    用于预测何时可以无序执行加载指令的方法和装置

    公开(公告)号：US5987595A

    公开(公告)日：1999-11-16

    申请号：US977546

    申请日：1997-11-25

    申请人： Adi Yoaz ,  Ronny Ronen ,  Robert C. Valentine

    发明人： Adi Yoaz ,  Ronny Ronen ,  Robert C. Valentine

    IPC分类号： G06F9/38 ,  G06F9/312

    CPC分类号： G06F9/3834 ,  G06F9/383 ,  G06F9/3838

    摘要： The invention in several embodiments includes an apparatus and a method for predicting whether store instructions can be safely executed out-of-order. The apparatus, includes at least one execution unit, a reorder buffer adapted to holding a plurality of instructions from an instruction sequence for execution by the execution units, and a memory storage device adapted to holding a collision history table. The collision history table has entries for load instructions of the instruction sequence Each of the entries is adapted to predicting when the associated load instruction is colliding.

    摘要翻译： 在几个实施例中的本发明包括一种用于预测存储指令是否可以无序安全执行的装置和方法。 该装置包括至少一个执行单元，适于从执行单元执行的指令序列保持多个指令的重排序缓冲器，以及适于保持冲突历史表的存储器存储装置。 冲突历史表具有用于指令序列的加载指令的条目每个条目适于预测何时相关联的加载指令相冲突。

    Mechanism for prefetching targets of memory de-reference operations in a high-performance processor
    6.
    发明授权
    Mechanism for prefetching targets of memory de-reference operations in a high-performance processor 失效
    在高性能处理器中预取存储器去引用操作的目标的机制

    公开(公告)号：US5822788A

    公开(公告)日：1998-10-13

    申请号：US771705

    申请日：1996-12-20

    申请人： Opher D. Kahn ,  Ilan Y. Spillinger ,  Adi Yoaz

    发明人： Opher D. Kahn ,  Ilan Y. Spillinger ,  Adi Yoaz

    IPC分类号： G06F9/355 ,  G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/355 ,  G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832

    摘要： A computer system provides enhanced performance when executing irregular code that include pointer de-reference operations. A memory controller of the computer system first fetches a pointer value from an address location in the memory and then calculates a new address adding a constant or scale factor to the pointer value. A logical-to-physical (i.e., virtual-to-physical) translation of the pointer value is also performed. The loading of data for the initial pointer load operation is overlapped with the de-reference operation, wherein the de-reference data is prefetched from memory using the resulting address and placed into the CPU's cache.

    摘要翻译： 当执行包括指针取消引用操作的不规则代码时，计算机系统提供增强的性能。 计算机系统的存储器控​​制器首先从存储器中的地址位置取出指针值，然后计算向指针值添加常数或比例因子的新地址。 还执行指针值的逻辑到物理（即虚拟到物理）的转换。 用于初始指针加载操作的数据的加载与解除参考操作重叠，其中使用所得到的地址从存储器预取去参考数据并将其放入CPU的高速缓存中。

    META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION
    8.
    发明申请
    META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION 有权
    META预测恢复检测故障

    公开(公告)号：US20130036297A1

    公开(公告)日：2013-02-07

    申请号：US13647153

    申请日：2012-10-08

    申请人： Stephan Jourdan ,  Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

    发明人： Stephan Jourdan ,  Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/3848

    摘要： Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 公开了在检测到分支或二进制错误预测时恢复元预测系统的方法和装置。 一个示例性装置可以包括一个基本错误预测历史寄存器，用于存储一组错误预测历史值，每个错误预测历史值指示是否正确或不正确地预测了由先前的分支指令取得的先前分支预测。 该装置可以包括元预测器，用于至少部分地基于基本错误预测历史寄存器的输出来检测当前分支预测的分支错误预测。 元预测器可以基于检测到分支错误预测来恢复基本的错误预测历史寄存器。 公开了附加装置，系统和方法。

    Method and apparatus for predicting branches using a meta predictor
    9.
    发明授权
    Method and apparatus for predicting branches using a meta predictor 有权
    使用元预测器预测分支的方法和装置

    公开(公告)号：US08285976B2

    公开(公告)日：2012-10-09

    申请号：US09749405

    申请日：2000-12-28

    申请人： Stephan J. Jourdan ,  Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

    发明人： Stephan J. Jourdan ,  Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

    IPC分类号： G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/3861 ,  G06F9/3848

    摘要： A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.

    摘要翻译： 公开了一种分支预测装置，其减少处理器中的分支错误预测。 分支预测装置包括基本错误预测历史寄存器。 分支预测装置包括元预测器，其接收索引值和分支预测，以根据基本错误预测历史寄存器生成错误预测值。 分支预测装置还包括接收分支预测和误预测值以产生最终预测的逻辑门。 最终预测可用于预测是否采取分支。

    Lookahead register value tracking
    10.
    发明授权
    Lookahead register value tracking 有权
    前瞻寄存器值跟踪

    公开(公告)号：US06742112B1

    公开(公告)日：2004-05-25

    申请号：US09473976

    申请日：1999-12-29

    申请人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

    发明人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

    IPC分类号： G06F934

    CPC分类号： G06F9/30134 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842

    摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

    摘要翻译： 跟踪寄存器值的装置和方法。 微处理器可以包括第一寄存器，控制电路和加法器。 第一个寄存器可以存储跟踪的寄存器值。 控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。 加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。