公开(公告)号：US08286111B2

公开(公告)日：2012-10-09

申请号：US12131821

申请日：2008-06-02

申请人： Rajit Chandra ,  John Yanjiang Shu ,  Adi Srinivasan ,  Paolo Carnevali

发明人： Rajit Chandra ,  John Yanjiang Shu ,  Adi Srinivasan ,  Paolo Carnevali

IPC分类号： G06F17/50

CPC分类号： G01K7/425 ,  G06F17/5036

摘要： A thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain static and/or transient thermal simulations of the chips based on thermal models and boundary conditions. The thermal simulations are performed in accordance with one or more grids, with boundaries and/or resolutions being determined by adaptive and/or hierarchical multi-dimensional techniques. The adaptive grid techniques include material-boundary, rate-of-change, and convergence-information heuristics. For example, a finer grid is used in a region having higher temperature gradients compared to a region having lower temperature gradients. The hierarchical grid techniques are based on critical, intermediate, and boundary regions specified manually or automatically, each region having a respective grid resolution. For example, a critical region is analyzed according to a grid that is finer than a grid of an intermediate region, and resolution of a grid of a boundary region is adapted to boundary conditions.

摘要翻译： 热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中，基于热模型和边界条件执行芯片的细粒度静态和/或瞬态热模拟。 根据一个或多个网格进行热模拟，其边界和/或分辨率由自适应和/或分级多维技术确定。 自适应网格技术包括物质边界，变化率和收敛信息启发式。 例如，与具有较低温度梯度的区域相比，在具有较高温度梯度的区域中使用更精细的栅格。 分级网格技术基于手动或自动指定的关键，中间和边界区域，每个区域具有相应的网格分辨率。 例如，根据比中间区域的网格更细的网格来分析临界区域，并且边界区域的网格的分辨率适合于边界条件。

公开(公告)号：US08019580B1

公开(公告)日：2011-09-13

申请号：US12101983

申请日：2008-04-12

申请人： Rajit Chandra ,  Paolo Carnevali ,  John Yanjiang Shu ,  Adi Srinivasan

发明人： Rajit Chandra ,  Paolo Carnevali ,  John Yanjiang Shu ,  Adi Srinivasan

IPC分类号： G06G7/48 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/16

摘要： Transient thermal simulation of semiconductor chips uses region-wise variable spatial grids and variable temporal intervals, enabling spatio-temporal thermal analysis of semiconductor chips. Temperature rates of change across a die and/or package of an integrated circuit are computed and tracked versus time. Critical time interval(s) for temperature evaluation are determined. Temperatures of elements, components, devices, and interconnects are updated based on a 3D full chip temperature analysis. Respective power dissipations are updated, as a function of the temperatures, with an automated interface to one or more circuit simulation tools. Subsequently new temperatures are determined as a function of the power dissipations. User definable control and observation parameters enable flexible and efficient transient thermal analysis. The parameters relate to power sources, monitoring, reporting, error tolerances, and output snapshots. Viewing of waveform plots and 3D spatial variations of temperature enable efficient communication of results of the thermal analysis with designers of integrated circuits.

摘要翻译： 半导体芯片的瞬态热模拟使用区域可变空间网格和可变时间间隔，实现半导体芯片的时空热分析。 对集成电路的管芯和/或封装的温度变化率进行计算并跟踪时间。 确定温度评估的临界时间间隔。 基于3D全芯片温度分析，更新元件，组件，设备和互连的温度。 通过与一个或多个电路仿真工具的自动化接口，可以随温度更新相应的功耗。 随后新的温度被确定为功率耗散的函数。 用户可定义的控制和观察参数可实现灵活高效的瞬态热分析。 这些参数与电源，监控，报告，容错和输出快照有关。 观察波形图和温度的三维空间变化可实现热分析结果与集成电路设计人员的高效沟通。

公开(公告)号：US20090024347A1

公开(公告)日：2009-01-22

申请号：US12131821

申请日：2008-06-02

申请人： Rajit Chandra ,  John Yanjiang Shu ,  Adi Srinivasan ,  Paolo Carnevali

发明人： Rajit Chandra ,  John Yanjiang Shu ,  Adi Srinivasan ,  Paolo Carnevali

IPC分类号： G01K3/00

CPC分类号： G01K7/425 ,  G06F17/5036

摘要： A thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain static and/or transient thermal simulations of the chips based on thermal models and boundary conditions. The thermal simulations are performed in accordance with one or more grids, with boundaries and/or resolutions being determined by adaptive and/or hierarchical multi-dimensional techniques. The adaptive grid techniques include material-boundary, rate-of-change, and convergence-information heuristics. For example, a finer grid is used in a region having higher temperature gradients compared to a region having lower temperature gradients. The hierarchical grid techniques are based on critical, intermediate, and boundary regions specified manually or automatically, each region having a respective grid resolution. For example, a critical region is analyzed according to a grid that is finer than a grid of an intermediate region, and resolution of a grid of a boundary region is adapted to boundary conditions.

摘要翻译： 热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中，基于热模型和边界条件执行芯片的细粒度静态和/或瞬态热模拟。 根据一个或多个网格进行热模拟，其边界和/或分辨率由自适应和/或分级多维技术确定。 自适应网格技术包括物质边界，变化率和收敛信息启发式。 例如，与具有较低温度梯度的区域相比，在具有较高温度梯度的区域中使用更细的栅格。 分级网格技术基于手动或自动指定的关键，中间和边界区域，每个区域具有相应的网格分辨率。 例如，根据比中间区域的网格更细的网格来分析临界区域，并且边界区域的网格的分辨率适合于边界条件。

公开(公告)号：US20090019411A1

公开(公告)日：2009-01-15

申请号：US12140188

申请日：2008-06-16

申请人： Rajit Chandra ,  Adi Srinivasan ,  Nanda Gopal

发明人： Rajit Chandra ,  Adi Srinivasan ,  Nanda Gopal

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/80 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/00014

摘要： In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions. The modeling optionally reads a mesh initialization file specifying selected aspects and parameters associated with controlling use and behavior of the variable grid spacing techniques.

摘要翻译： 在第一种变型中，热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中，基于热模型和边界条件执行芯片的细粒度热模拟。 该套件使用模拟结果来修改热显着结构，以实现跨芯片所需的热变化，满足芯片选定部分的设计断言，并验证芯片在指定工作范围和制造变化方面的整体性能和可靠性。 在第二个变体中，离散化方法使用启发式将芯片温度分布建模成三维自适应网格空间。 自适应和局部可变网格间距技术用于有效和准确地收敛稳态和/或瞬态温度解。 该建模可选地读取指定与控制可变网格间距技术的使用和行为相关联的所选方面和参数的网格初始化文件。

公开(公告)号：US07353471B1

公开(公告)日：2008-04-01

申请号：US11198470

申请日：2005-08-05

申请人： Rajit Chandra ,  Adi Srinivasan

发明人： Rajit Chandra ,  Adi Srinivasan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5009 ,  G06F2217/78 ,  G06F2217/80

摘要： A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.

摘要翻译： 公开了一种使用半导体芯片设计的全芯片热分析来计算热导率的方法和装置。 用于分析包括多个物理层的半导体芯片设计的导电性的新方法的一个实施例包括限定多个物理层内的至少一个热层，其中热层代表热导率的变化相对 到半导体芯片设计的其余部分，并计算热层的热导率。 由于热层表示半导体芯片设计上的热导率的变化，热层不一定对应于半导体芯片设计的物理层一一对应。 因此，可以从热层计算半导体芯片设计中的热导率。

公开(公告)号：US20080141192A1

公开(公告)日：2008-06-12

申请号：US12016467

申请日：2008-01-18

申请人： RAJIT CHANDRA ,  Adi Srinivasan

发明人： RAJIT CHANDRA ,  Adi Srinivasan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5009 ,  G06F2217/78 ,  G06F2217/80

摘要： A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.

摘要翻译： 公开了一种使用半导体芯片设计的全芯片热分析来计算热导率的方法和装置。 用于分析包括多个物理层的半导体芯片设计的导电性的新方法的一个实施例包括限定多个物理层内的至少一个热层，其中热层代表热导率的变化相对 到半导体芯片设计的其余部分，并计算热层的热导率。 由于热层表示半导体芯片设计上的热导率的变化，热层不一定对应于半导体芯片设计的物理层一一对应。 因此，可以从热层计算半导体芯片设计中的热导率。

公开(公告)号：US07823102B2

公开(公告)日：2010-10-26

申请号：US12140188

申请日：2008-06-16

申请人： Rajit Chandra ,  Adi Srinivasan ,  Nanda Gopal

发明人： Rajit Chandra ,  Adi Srinivasan ,  Nanda Gopal

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5031 ,  G06F17/5036 ,  G06F17/5072 ,  G06F2217/80 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/00014

摘要： In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions. The modeling optionally reads a mesh initialization file specifying selected aspects and parameters associated with controlling use and behavior of the variable grid spacing techniques.

摘要翻译： 在第一种变型中，热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中，基于热模型和边界条件执行芯片的细粒度热模拟。 该套件使用模拟结果来修改热显着结构，以实现芯片上所需的热变化，满足芯片选定部分的设计断言，并验证芯片在指定工作范围和制造变化方面的整体性能和可靠性。 在第二个变体中，离散化方法使用启发式将芯片温度分布建模成三维自适应网格空间。 自适应和局部可变网格间距技术用于有效和准确地收敛稳态和/或瞬态温度解。 该建模可选地读取指定与控制可变网格间距技术的使用和行为相关联的所选方面和参数的网格初始化文件。

公开(公告)号：US5367482A

公开(公告)日：1994-11-22

申请号：US110682

申请日：1993-08-23

申请人： Ta-Pen Guo ,  Adi Srinivasan

发明人： Ta-Pen Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356156 ,  G11C11/412

摘要： A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

摘要翻译： 电平移动静态随机存取存储单元包括具有第一P沟道MOS晶体管的第一级，其第一P沟道MOS晶体管的源极连接到高压电源轨，漏极连接到第一N沟道MOS晶体管的漏极。 第一N沟道MOS晶体管的源极连接到第二N沟道MOS晶体管的漏极。 第二N沟道MOS晶体管的源极连接到VSS电源轨。 第二级包括其源极连接到高压电源轨VHS的第二P沟道MOS晶体管，其漏极连接到第三N沟道MOS晶体管的漏极。 第三N沟道MOS晶体管的源极连接到第四N沟道MOS晶体管的漏极。 第四个N沟道MOS晶体管的源极连接到VSS。 第一和第二P沟道MOS晶体管的栅极交叉耦合，并且第二和第四N沟道MOS晶体管的栅极交叉耦合。 第一和第三N沟道MOS晶体管的栅极连接到电源轨VDD，通常为5伏。 第一和第二P沟道MOS晶体管形成在电压为VHS的n阱偏置中。 通过第五N沟道MOS晶体管耦合到第二N沟道MOS晶体管的漏极的位线，其栅极连接到字线。

公开(公告)号：US5239503A

公开(公告)日：1993-08-24

申请号：US900241

申请日：1992-06-17

申请人： Ta-Pen Guo ,  Adi Srinivasan

发明人： Ta-Pen Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  H03K3/356

CPC分类号： H03K3/356156 ,  G11C11/412

摘要： A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

公开(公告)号：US06701507B1

公开(公告)日：2004-03-02

申请号：US10022751

申请日：2001-12-14

申请人： Adi Srinivasan

发明人： Adi Srinivasan

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for computing a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver is described. The zero-skew driver insertion point is the position in the area where the spread of the signal arrival times at the nodes driven by the driver is minimized. The method includes: expressing a function describing a distance from each of the nodes to the zero-skew driver insertion point, expressing the variance of the function, minimizing the variance of the function, and solving an equation representative of the minimization of the variance of the function to determine the position of the zero-skew driver insertion point. In one embodiment, the minimizing the variance of the function includes: taking a first derivative of the function with respect to the distance, and setting the first derivative of the function to zero.

摘要翻译： 描述了用于计算由驾驶员驱动的节点占据的区域中的零倾斜驱动器插入点的位置的方法。 零偏移驱动器插入点是在由驱动器驱动的节点处的信号到达时间的扩展最小化的区域中的位置。 该方法包括：表达描述从每个节点到零偏移驱动器插入点的距离的函数，表示函数的方差，最小化函数的方差，以及求解表示方差最小化的方程 确定零倾斜驱动器插入点位置的功能。 在一个实施例中，使函数的方差最小化包括：相对于距离获取函数的一阶导数，并将函数的一阶导数设置为零。