公开(公告)号：US5420069A

公开(公告)日：1995-05-30

申请号：US999245

申请日：1992-12-31

申请人： Rajiv V. Joshi ,  Manu J. Tejwani ,  Kris V. Srikrishnan

发明人： Rajiv V. Joshi ,  Manu J. Tejwani ,  Kris V. Srikrishnan

IPC分类号： H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76852 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/49866 ,  H01L23/53233 ,  H01L2924/0002

摘要： The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

摘要翻译： 公开了耐蚀Cu / Cu（x）Ge（y）合金或Cu / Cu3Ge相双层互连金属线的制造和使用。 描述了在200-450℃的温度下在CVD反应器中使GeH 4气体与Cu表面在低压下反应形成Cu 3 Ge相或Cu（x）Ge（y）合金的固态选择性过程。 通过本发明的Cu / Cu3Ge相或CuxGey合金双层，现在可以实现铜互连的腐蚀问题的耐腐蚀半导体器件和封装互连。 提出了铜通孔完全或部分转化为Cu3Ge或CuxGey的结构。 此外，不同的金属如Al-Cu可以通过Cu3Ge相或CuxGey合金填充的通孔连接，以提高电迁移性能。

公开(公告)号：US08767501B2

公开(公告)日：2014-07-01

申请号：US13550762

申请日：2012-07-17

申请人： Rajiv V. Joshi ,  Ajay N. Bhoj

发明人： Rajiv V. Joshi ,  Ajay N. Bhoj

IPC分类号： G11C8/10

CPC分类号： G06F12/0864 ,  G06F2212/1021 ,  G11C15/04

摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.

摘要翻译： 关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。 可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。 可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。 对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。 采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作 错过率。 地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

公开(公告)号：US08578316B1

公开(公告)日：2013-11-05

申请号：US13607678

申请日：2012-09-08

申请人： Rajiv V. Joshi ,  Ajay N. Bhoj

发明人： Rajiv V. Joshi ,  Ajay N. Bhoj

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5018

摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

公开(公告)号：US20130289965A1

公开(公告)日：2013-10-31

申请号：US13457722

申请日：2012-04-27

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

公开(公告)号：US20130289948A1

公开(公告)日：2013-10-31

申请号：US13611359

申请日：2012-09-12

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。

公开(公告)号：US20130042217A1

公开(公告)日：2013-02-14

申请号：US13205186

申请日：2011-08-08

申请人： Fook-Luen HENG ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

发明人： Fook-Luen HENG ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

摘要翻译： 迁移电路布局的方法和系统。 使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。 通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在平面图布局上使用基于形状约束的缩放。 细胞被放置在由平面图布局定义的位置处。 使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

公开(公告)号：US08214777B2

公开(公告)日：2012-07-03

申请号：US12419377

申请日：2009-04-07

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G01R31/025 ,  G11C29/006 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2029/5602

摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

摘要翻译： 泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。 与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流， 类型设备已超过阈值。 测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

公开(公告)号：US07994042B2

公开(公告)日：2011-08-09

申请号：US11924735

申请日：2007-10-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US07968944B2

公开(公告)日：2011-06-28

申请号：US12541641

申请日：2009-08-14

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US07911025B2

公开(公告)日：2011-03-22

申请号：US12127080

申请日：2008-05-27

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。