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公开(公告)号：US06967664B1
公开(公告)日：2005-11-22
申请号：US09552932
申请日：2000-04-20
申请人： Ralph C. Taylor , Michael Mantor , Michael A. Mang
发明人： Ralph C. Taylor , Michael Mantor , Michael A. Mang
IPC分类号： G09G5/02
CPC分类号： G06T15/30
摘要： A method and apparatus for processing graphics primitives that includes a trivial discard guard band. Such a trivial discard guard band is used for comparison operations with the vertices of graphics primitives to determine whether the graphics primitives can be trivially discarded such that no further processing of the primitives is performed. The trivial discard guard band may be based on the specific dimensions of primitives such as one-half of the width of the line primitives or the radial dimension of point primitives such that the rasterization area of such primitives is taken into account when trivial discard decisions are performed.
摘要翻译： 一种用于处理包括平凡丢弃保护带的图形图元的方法和装置。 这样一个平凡的丢弃保护带用于与图形基元的顶点的比较操作，以确定是否可以平均地丢弃图形基元，使得不执行对图元的进一步处理。 平凡的丢弃保护带可以基于诸如线基元的宽度的一半或点基元的径向尺寸的基元的特定尺寸，使得当简单的丢弃决定是这样的原理时，考虑到这样的图元的光栅化区域 执行。
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公开(公告)号：US06784888B2
公开(公告)日：2004-08-31
申请号：US09969669
申请日：2001-10-03
IPC分类号： G06T1500
CPC分类号： G06F9/3001 , G06F9/3017 , G06T15/005
摘要： The occurrence of an (n+m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In turn, the PVS controller provides at least two substitute instructions, neither of which requires more than n operands from the n output data source, to a PVS engine. A first of the substitute instructions is executed by the PVS engine to provide an intermediate result that is temporarily stored and used as an input to another of the at least two substitute instructions. In this manner, the present invention avoids the expense of additional or significantly modified memory. In one embodiment of the present invention, a pre-accumulator register internal to the PVS engine is used to store the intermediate result. In this manner, the present invention provides a relatively inexpensive solution for a relatively infrequent occurrence.
摘要翻译： 可编程顶点着色器（PVS）控制器识别需要从n输出数据源输入操作数大于n的（n + m）个输入操作数指令。 反过来，PVS控制器提供至少两个替代指令，这两个指令都不需要n个输出数据源的n个操作数到PVS引擎。 替代指令中的第一个由PVS引擎执行，以提供临时存储的中间结果，并将其用作至少两个替代指令中的另一个的输入。 以这种方式，本发明避免了附加或显着修改的存储器的费用。 在本发明的一个实施例中，PVS引擎内部的预累加器寄存器用于存储中间结果。 以这种方式，本发明提供了相对不频繁发生的相对便宜的解决方案。
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3.发明授权Method and apparatus for clipping an object element in accordance with a clip volume 有权用于根据剪辑音量剪切对象元素的方法和装置公开(公告)号：US06507348B1
公开(公告)日：2003-01-14
申请号：US09496732
申请日：2000-02-02
IPC分类号： G06T1530
CPC分类号： G06T15/30
摘要： A method and apparatus for clipping an object element include processing that begins by ascribing barycentric coordinates to each original vertices of an object-element wherein each barycentric coordinate is a weighting factor with respect to a corresponding original vertex. The processing continues by obtaining clipping distances for each original vertex with respect to a clipping plane. For a new vertex of an object-element that represents an intersection of an edge of the object-element with the clipping plane, the process continues by determining a barycentric coordinate for the new vertex. The determination of the new vertex is based on the barycentric coordinates of the original vertices defining the edge and the clipping distances. Having determined the barycentric coordinates for the new vertices corresponding to a clipping plane, the process is repeated for each of a plurality of other clipping planes that intersect the object-element. Once all of the clipping planes have been processed, the attributes for the resulting clipped object element are calculated based on the barycentric coordinates of the vertices defining the clipped object element and the attributes of the original vertices.
摘要翻译： 用于剪切对象元素的方法和装置包括通过将重心坐标归因于对象元素的每个原始顶点开始的处理，其中每个重心坐标是相对于相应的原始顶点的加权因子。 通过相对于剪切平面获得每个原始顶点的剪切距离来继续处理。 对于表示对象元素的边缘与剪切平面的交集的对象元素的新顶点，该过程通过确定新顶点的重心坐标而继续。 新顶点的确定是基于限定边缘的原始顶点和剪切距离的重心坐标。 确定了与剪切平面相对应的新顶点的重心坐标时，对于与对象元素相交的多个其他裁剪平面中的每一个重复该过程。 一旦已经处理了所有剪切平面，则基于定义剪切对象元素的顶点的重心坐标和原始顶点的属性来计算所生成的剪切对象元素的属性。
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公开(公告)号：US20110050716A1
公开(公告)日：2011-03-03
申请号：US12691541
申请日：2010-01-21
IPC分类号： G09G5/00
CPC分类号： G06T15/005
摘要： A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines.
摘要翻译： 处理器包括第一着色引擎和第二着色引擎。 第一个着色引擎被配置为处理要在显示设备上显示的第一子像素的像素着色器。 第二着色引擎被配置为处理要显示在显示设备上的第二像素子像素的像素着色器。 第一和第二着色引擎都配置为处理通用计算着色器和非像素图形着色器。 处理器还可以包括耦合到第一和第二着色引擎之间并定位在第一和第二着色引擎之间的一级（L1）数据高速缓存。
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公开(公告)号：US09142057B2
公开(公告)日：2015-09-22
申请号：US12691541
申请日：2010-01-21
CPC分类号： G06T15/005
摘要： A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines.
摘要翻译： 处理器包括第一着色引擎和第二着色引擎。 第一个着色引擎被配置为处理要在显示设备上显示的第一子像素的像素着色器。 第二着色引擎被配置为处理要显示在显示设备上的第二像素子像素的像素着色器。 第一和第二着色引擎都配置为处理通用计算着色器和非像素图形着色器。 处理器还可以包括耦合到第一和第二着色引擎之间并定位在第一和第二着色引擎之间的一级（L1）数据高速缓存。
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公开(公告)号：US06943800B2
公开(公告)日：2005-09-13
申请号：US09928754
申请日：2001-08-13
申请人： Ralph C. Taylor , Michael J. Mantor
发明人： Ralph C. Taylor , Michael J. Mantor
摘要： In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.
摘要翻译： 在图形处理电路中，多达N组状态数据被存储在缓冲器中，使得N组状态数据的总长度不超过缓冲器的总长度。 当一长度的附加状态数据将超过缓冲器中的可用空间的长度时，缓冲器中的附加状态数据集的存储被延迟，直到N组状态数据的至少M不再被用于处理图形 原语，其中M小于或等于N.缓冲器优选地实现为环形缓冲器，从而最小化状态数据更新的影响。 为了进一步防止状态数据的破坏，如果缓冲器中已经存储了最大数量的允许状态，则禁止将附加的状态数据组添加到缓冲器中。
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公开(公告)号：US20120019541A1
公开(公告)日：2012-01-26
申请号：US12839965
申请日：2010-07-20
申请人： Vineet Goel , Ralph C. Taylor , Todd E. Martin
发明人： Vineet Goel , Ralph C. Taylor , Todd E. Martin
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： Disclosed herein is a vertex core. The vertex core includes a grouper module configured to process two or more primitives during one clock period and two or more vertex translators configured to respectively receive the two or more processed primitives in parallel.
摘要翻译： 这里公开了顶点核心。 顶点核心包括被配置为在一个时钟周期期间处理两个或多个基元的分层器模块，以及被配置为分别并行地接收两个或多个处理的原语的两个或多个顶点翻译器。
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公开(公告)号：US07594069B2
公开(公告)日：2009-09-22
申请号：US10788225
申请日：2004-02-26
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0844 , G06F12/0875
摘要： An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.
摘要翻译： 用于单指令多数据缓存的装置和方法包括可操作以接收主要访问请求的存储器访问请求发生器。 所述方法和装置还包括耦合到存储器访问请求生成器的高速缓存控制器，其中高速缓存控制器可操作以执行存储器请求。 所述方法和装置还包括耦合到所述高速缓存控制器的存储器接口，所述存储器接口可操作以检索多个所请求的数据。 该方法和装置还包括耦合到高速缓存控制器，存储器接口和存储器访问请求生成器的请求处理器。 请求处理器可操作以接收多个所请求的数据，并随后从其生成多个并行数据输出。
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