公开(公告)号：US11763865B1

公开(公告)日：2023-09-19

申请号：US17458215

申请日：2021-08-26

Applicant: Rambus Inc.

Inventor： Andrew Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US11127444B1

公开(公告)日：2021-09-21

申请号：US16995612

申请日：2020-08-17

Applicant: Rambus Inc.

Inventor： Andrew Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

IPC: G11C7/22 ,  G11C7/10

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

公开(公告)号：US20220255550A1

公开(公告)日：2022-08-11

申请号：US17590668

申请日：2022-02-01

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Andrew Fuller ,  Hsuan-Jung Su

IPC: H03K19/094 ,  G01R31/3193 ,  G11C11/4076 ,  G11C7/10

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

公开(公告)号：US20240171368A1

公开(公告)日：2024-05-23

申请号：US18507288

申请日：2023-11-13

Applicant: Rambus Inc.

Inventor： Andrew Fuller

IPC: H04L7/00

CPC classification number: H04L7/0054

Abstract: A lock-detection circuit detects whether a first clock signal is frequency locked to a second clock signal. A lock-detection scheme that continuously evaluates the lock condition between the clock signals and as programmable frequency-offset tolerances for reporting lock acquisition and loss. A quadrature clock generator produces two periodic signals from the first clock signal. The periodic signals are in quadrature, which is to say they are misaligned with one another by ninety degrees. These quadrature signals are sampled on edges of the second clock signal to produce a sequence of states that exhibit a Gray-code progression if first and second clock signals are locked. Errors in the Gray-code progression indicate whether edges of the first clock signal are early or late with respect to the second clock signal. The lock-detection circuit is adjustable to indicate loss of lock under in dependence upon the temporal spacing of errors.

公开(公告)号：US11955971B2

公开(公告)日：2024-04-09

申请号：US17590668

申请日：2022-02-01

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Andrew Fuller ,  Hsuan-Jung Su

IPC: G11C7/10 ,  G01R31/3193 ,  G11C11/4076 ,  H03K19/094

CPC classification number: H03K19/09429 ,  G01R31/31937 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.