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    DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT
    3.
    发明申请
    DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT 有权
    分布式片上解码设备和使用包互连的方法

    公开(公告)号：US20150221589A1

    公开(公告)日：2015-08-06

    申请号：US14683073

    申请日：2015-04-09

    Applicant: Rambus Inc.

    Inventor： David Secker ,  Ling Yang ,  Chanh Tran ,  Ying Ji

    IPC: H01L23/528 ,  H03K5/1252 ,  H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06541 ,  H01L2924/00014 ,  H03K5/1252 ,  H01L2224/0401

    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

    Abstract translation: 公开了一种集成电路器件。 集成电路器件包括通过前端半导体工艺制造并具有相对布置的平坦表面的半导体管芯。 半导体管芯由半导体器件，耦合到半导体器件的电源电路，去耦电容电路和通孔形成。 通孔包括耦合到电源电路的第一组通孔和耦合到去耦电容电路的第二组通孔。 根据后端半导体工艺，在设置在半导体管芯上的第一金属层中形成导体。 导体被配置为耦合到第一组和第二组通孔，以建立从电源电路到去耦电容电路的导电路径。

    Distributed on-chip decoupling apparatus and method using package interconnect
    4.
    发明授权
    Distributed on-chip decoupling apparatus and method using package interconnect 有权
    分布式片上去耦装置和使用封装互连的方法

    公开(公告)号：US09006907B2

    公开(公告)日：2015-04-14

    申请号：US13903323

    申请日：2013-05-28

    Applicant: Rambus Inc.

    Inventor： David Secker ,  Ling Yang ,  Chanh Tran ,  Ying Ji

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/18 ,  H01L23/522 ,  H01L23/498

    CPC classification number: H01L23/481 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06541 ,  H01L2924/00014 ,  H03K5/1252 ,  H01L2224/0401

    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

    Abstract translation: 公开了一种集成电路器件。 集成电路器件包括通过前端半导体工艺制造并具有相对布置的平坦表面的半导体管芯。 半导体管芯由半导体器件，耦合到半导体器件的电源电路，去耦电容电路和通孔形成。 通孔包括耦合到电源电路的第一组通孔和耦合到去耦电容电路的第二组通孔。 根据后端半导体工艺，在设置在半导体管芯上的第一金属层中形成导体。 导体被配置为耦合到第一组和第二组通孔，以建立从电源电路到去耦电容电路的导电路径。

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