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公开(公告)号：US11742874B2
公开(公告)日：2023-08-29
申请号：US18070694
申请日：2022-11-29
Applicant: Rambus Inc.
Inventor： Ravi Shivnaraine , Marcus Van Ierssel
CPC classification number: H03M1/68
Abstract: A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.
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公开(公告)号：US10855297B2
公开(公告)日：2020-12-01
申请号：US16441742
申请日：2019-06-14
Applicant: Rambus Inc.
Inventor： Marcus Van Ierssel , Dominic Diclemente
Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.
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公开(公告)号：US11601151B2
公开(公告)日：2023-03-07
申请号：US17106641
申请日：2020-11-30
Applicant: Rambus Inc.
Inventor： Nanyan Wang , Marcus Van Ierssel
IPC: H04B1/16
Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.
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公开(公告)号：US11671286B2
公开(公告)日：2023-06-06
申请号：US17298165
申请日：2019-12-10
Applicant: Rambus Inc.
Inventor： Mohammad Sadegh Jalali , Marcus Van Ierssel
IPC: H04L25/03
CPC classification number: H04L25/03267 , H04L25/03057 , H04L25/03146
Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.
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公开(公告)号：US11206031B2
公开(公告)日：2021-12-21
申请号：US17082467
申请日：2020-10-28
Applicant: Rambus Inc.
Inventor： Marcus Van Ierssel , Dominic DiClemente
Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.
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Patent Agency Ranking
公开(公告)号：US20170346618A1
公开(公告)日：2017-11-30
申请号：US15629453
申请日：2017-06-21
Applicant: Rambus Inc.
Inventor： Mehrdad Ramezani , David J. Cassan , Christopher D. Holdenried , Sang-Wook Paul Park , Marcus Van Ierssel
CPC classification number: H04L7/0087 , H03L7/081 , H04L7/0029 , H04L7/0079 , H04L7/0331 , H04L7/0337 , H04L25/03057
Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
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公开(公告)号：US11671108B2
公开(公告)日：2023-06-06
申请号：US17728607
申请日：2022-04-25
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer , Marcus Van Ierssel
CPC classification number: H03M1/1023 , H03M1/0639 , H03M1/46
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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公开(公告)号：US11342929B2
公开(公告)日：2022-05-24
申请号：US17262901
申请日：2019-07-30
Applicant: Rambus Inc.
Inventor： Kenneth C. Dyer , Marcus Van Ierssel
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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公开(公告)号：US10211972B2
公开(公告)日：2019-02-19
申请号：US15629453
申请日：2017-06-21
Applicant: Rambus Inc.
Inventor： Mehrdad Ramezani , David J. Cassan , Christopher D. Holdenried , Sang-Wook Paul Park , Marcus Van Ierssel
Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
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公开(公告)号：US11569975B2
公开(公告)日：2023-01-31
申请号：US17333380
申请日：2021-05-28
Applicant: Rambus Inc.
Inventor： Marcus Van Ierssel
Abstract: A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.
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