公开(公告)号：US12093180B2

公开(公告)日：2024-09-17

申请号：US17853735

申请日：2022-06-29

申请人： Rambus Inc.

发明人： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

CPC分类号： G06F12/0868 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20210326265A1

公开(公告)日：2021-10-21

申请号：US17221639

申请日：2021-04-02

申请人： Rambus Inc.

发明人： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US10970220B2

公开(公告)日：2021-04-06

申请号：US16450782

申请日：2019-06-24

申请人： Rambus Inc.

发明人： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20190391921A1

公开(公告)日：2019-12-26

申请号：US16450782

申请日：2019-06-24

申请人： Rambus Inc.

发明人： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20230418758A1

公开(公告)日：2023-12-28

申请号：US18214450

申请日：2023-06-26

申请人： Rambus Inc.

发明人： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F9/38 ,  G06F12/0864

CPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F9/3816 ,  G06F12/0864

摘要： A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

公开(公告)号：US11726920B2

公开(公告)日：2023-08-15

申请号：US16453284

申请日：2019-06-26

申请人： Rambus Inc.

发明人： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0864 ,  G06F9/38

CPC分类号： G06F12/0895 ,  G06F9/3816 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0864

摘要： A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.

公开(公告)号：US20220398198A1

公开(公告)日：2022-12-15

申请号：US17853735

申请日：2022-06-29

申请人： Rambus Inc.

发明人： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US11409659B2

公开(公告)日：2022-08-09

申请号：US17221639

申请日：2021-04-02

申请人： Rambus Inc.

发明人： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20200004686A1

公开(公告)日：2020-01-02

申请号：US16453284

申请日：2019-06-26

申请人： Rambus Inc.

发明人： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0895 ,  G06F12/0804 ,  G06F12/0864 ,  G06F9/38 ,  G06F12/0815

摘要： A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.