公开(公告)号：US11687247B2

公开(公告)日：2023-06-27

申请号：US17339683

申请日：2021-06-04

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/14 ,  G11C14/00 ,  G11C5/04 ,  G11C11/00 ,  G06F13/16 ,  G06F11/00 ,  G11C7/10 ,  G06F11/14

CPC classification number: G06F3/0613 ,  G06F3/065 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F12/1441 ,  G06F13/1673 ,  G11C5/04 ,  G11C11/005 ,  G11C14/0009 ,  G06F11/14 ,  G06F13/1668 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C7/1051 ,  Y02D10/00

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20210357131A1

公开(公告)日：2021-11-18

申请号：US17339683

申请日：2021-06-04

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20190042105A1

公开(公告)日：2019-02-07

申请号：US16042374

申请日：2018-07-23

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G11C11/00 ,  G11C5/04 ,  G06F13/16 ,  G06F12/0802 ,  G06F11/00 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F12/1441 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C5/04 ,  G11C7/1051 ,  G11C11/005 ,  G11C14/0009 ,  Y02D10/14

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US11347587B2

公开(公告)日：2022-05-31

申请号：US16881859

申请日：2020-05-22

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Stephen Magee ,  John Eric Linstadt

IPC: G06F11/10 ,  G06F3/06

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US10970220B2

公开(公告)日：2021-04-06

申请号：US16450782

申请日：2019-06-24

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20200034046A1

公开(公告)日：2020-01-30

申请号：US16535814

申请日：2019-08-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20190391921A1

公开(公告)日：2019-12-26

申请号：US16450782

申请日：2019-06-24

Applicant: Rambus Inc.

Inventor： Michael Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US10379752B2

公开(公告)日：2019-08-13

申请号：US16042374

申请日：2018-07-23

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16 ,  G11C7/10

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US12147345B2

公开(公告)日：2024-11-19

申请号：US18074217

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

IPC: G06F12/08 ,  G06F12/0815 ,  G11C14/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

公开(公告)号：US20230135017A1

公开(公告)日：2023-05-04

申请号：US18074217

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

IPC: G06F12/0815 ,  G11C14/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.