公开(公告)号：US12204758B2

公开(公告)日：2025-01-21

申请号：US18235068

申请日：2023-08-17

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06 ,  G06F13/00 ,  G06F13/16

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US11733870B2

公开(公告)日：2023-08-22

申请号：US16249109

申请日：2019-01-16

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/00 ,  G06F13/1642

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US10185499B1

公开(公告)日：2019-01-22

申请号：US14536312

申请日：2014-11-07

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

公开(公告)号：US20240028207A1

公开(公告)日：2024-01-25

申请号：US18235068

申请日：2023-08-17

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F3/0611 ,  G06F13/1642 ,  G06F13/00 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.