-
公开(公告)号：US12205669B2
公开(公告)日：2025-01-21
申请号：US18513473
申请日：2023-11-17
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
-
公开(公告)号：US11854658B2
公开(公告)日：2023-12-26
申请号：US17696818
申请日：2022-03-16
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
CPC classification number: G11C7/1072 , G06F11/073 , G06F11/0778 , G06F11/0787 , G06F11/1044 , G06F11/1048 , G06F11/1068 , G11C7/1006 , G06F11/1008 , G11C5/04 , G11C29/52 , G11C2029/0411
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
-
公开(公告)号：US10607669B2
公开(公告)日：2020-03-31
申请号：US15978344
申请日：2018-05-14
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
-
公开(公告)号：US20190243544A1
公开(公告)日：2019-08-08
申请号：US16266216
申请日：2019-02-04
Applicant: Rambus Inc.
Inventor： David Wang
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F13/00 , G06F13/1689
Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
-
公开(公告)号：US20240028207A1
公开(公告)日：2024-01-25
申请号：US18235068
申请日：2023-08-17
Applicant: Rambus Inc.
Inventor： David Wang , Nirmal Saxena
CPC classification number: G06F3/0611 , G06F13/1642 , G06F13/00 , G06F3/0625 , G06F3/0659 , G06F3/0673
Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.
-
Patent Agency Ranking
公开(公告)号：US11282552B2
公开(公告)日：2022-03-22
申请号：US16831121
申请日：2020-03-26
Applicant: Rambus Inc.
Inventor： Christopher Haywood , David Wang
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
-
公开(公告)号：US10198187B1
公开(公告)日：2019-02-05
申请号：US14885031
申请日：2015-10-16
Applicant: Rambus Inc.
Inventor： David Wang
IPC: G06F3/06
Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
-
公开(公告)号：US20240161795A1
公开(公告)日：2024-05-16
申请号：US18513473
申请日：2023-11-17
Applicant: Rambus Inc.
Inventor： Christopher HAYWOOD , David Wang
CPC classification number: G11C7/1072 , G06F11/073 , G06F11/0778 , G06F11/0787 , G06F11/1044 , G06F11/1048 , G06F11/1068 , G11C7/1006 , G11C29/52
Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.
-
公开(公告)号：US20200293190A1
公开(公告)日：2020-09-17
申请号：US16831130
申请日：2020-03-26
Applicant: Rambus Inc.
Inventor： David Wang
Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
-
公开(公告)号：US10606483B2
公开(公告)日：2020-03-31
申请号：US16266216
申请日：2019-02-04
Applicant: Rambus Inc.
Inventor： David Wang
Abstract: In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.022 seconds)
