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    Adaptive signal termination
    2.
    发明申请
    Adaptive signal termination 有权
    自适应信号终止

    公开(公告)号：US20040201402A1

    公开(公告)日：2004-10-14

    申请号：US10800192

    申请日：2004-03-12

    申请人： Rambus Inc.

    发明人： Suresh Rajan ,  Scott Best

    IPC分类号： H03K017/16

    CPC分类号： H04L25/0278 ,  H04L25/0292

    摘要： An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.

    摘要翻译： 输入信号从第一设备发送到第二设备。 在第二装置处接收输入信号方法，并且响应于输入信号产生输出信号。 感测输出信号，响应感测输出数据，输入信号被动态地终止。 在一些实施例中，接收，产生和动态终止发生在单个集成电路内。 在一些实施例中，该方法包括检测输入信号的信号电压电平，并且响应于信号电压电平使终端电压电平从第一电压电平变为第二电压电平。

    Apparatus and method for a digital delay locked loop
    3.
    发明申请
    Apparatus and method for a digital delay locked loop 失效
    数字延迟锁定环的装置和方法

    公开(公告)号：US20040046597A1

    公开(公告)日：2004-03-11

    申请号：US10658710

    申请日：2003-09-08

    申请人： RAMBUS INC.

    发明人： Elad Alon ,  Scott Best

    IPC分类号： H03H011/26

    CPC分类号： H03K3/037 ,  H03K3/0375 ,  H03L7/0802 ,  H03L7/0814

    摘要： A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a received clock signal. An output tap from one delay line is used to produce a rising edge in an output clock signal while a corresponding tap in the complementary delay line is used to produce a falling edge in the output signal in order to correct for distortion. The MUXes are controlled based on a phase difference detected between the received clock signal and a feedback clock corresponding to the output clock signal. Another aspect of the present invention provides for generation of a quadrature clock by interpolating between the rising and falling edges selected for the output clock signal. Still another aspect of the present invention provides for selectively disabling unused elements of the delay lines to reduce power consumption.

    摘要翻译： 示出了延迟锁定环（DLL）系统中的延迟线的数字控制的电路和方法。 一对多路复用器（MUX）用于从延迟参考时钟信号的一对互补延迟线中选择输出抽头，以便锁定到所接收的时钟信号上。 来自一个延迟线的输出抽头用于产生输出时钟信号中的上升沿，而互补延迟线中的相应抽头用于在输出信号中产生下降沿以便校正失真。 基于在接收的时钟信号和对应于输出时钟信号的反馈时钟之间检测到的相位差来控制MUX。 本发明的另一方面提供了通过在为输出时钟信号选择的上升沿和下降沿之间进行内插来产生正交时钟。 本发明的另一方面提供了选择性地禁用延迟线的未使用元件以降低功耗。

    METHOD AND APPARATUS FOR SELECTABLY PROVIDING SINGLE-ENDED AND DIFFERENTIAL SIGNALING WITH CONTROLLABLE IMPEDANCE AND TRANSITION TIME
    4.
    发明申请
    METHOD AND APPARATUS FOR SELECTABLY PROVIDING SINGLE-ENDED AND DIFFERENTIAL SIGNALING WITH CONTROLLABLE IMPEDANCE AND TRANSITION TIME 有权
    用于选择性提供具有可控阻力和转换时间的单端和差分信号的方法和装置

    公开(公告)号：US20040000924A1

    公开(公告)日：2004-01-01

    申请号：US10079143

    申请日：2002-02-19

    申请人： Rambus, Inc.

    发明人： Scott Best ,  Chiping Yang

    IPC分类号： H03K019/003

    CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H03K17/164 ,  H03K19/018585 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/085 ,  H04L25/45

    摘要： A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the type of termination selected, a capability for dynamic control of the termination impedance is provided. Moreover, an ability to change impedances of termination elements to maintain a desired termination impedance for both single-reference termination and center termination modes by shifting bits is provided. Also, a capability for dynamic control of transition times of signals is provided.

    摘要翻译： 提供了一种可选择地提供具有可控阻抗和转换时间的单端和差分信号的方法和装置。 根据该方法和装置，差分信号可以通过两条线路传输，或者两条单端信号可以通过两条线路传输。 根据该方法和装置，可以在单参考终端，中心终端或高阻抗终端中选择终止。 不管选择的终端类型如何，都提供了终端阻抗的动态控制能力。 此外，提供了通过移位来改变端接元件的阻抗以维持单参考端接和中心端接模式的期望的终端阻抗的能力。 此外，还提供了用于动态控制信号的转换时间的能力。