公开(公告)号：US20240345745A1

公开(公告)日：2024-10-17

申请号：US18643662

申请日：2024-04-23

申请人： Rambus Inc.

发明人： Thomas Vogelsang ,  Brent Steven Haukness

IPC分类号： G06F3/06

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

摘要： A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

公开(公告)号：US12105975B2

公开(公告)日：2024-10-01

申请号：US18230413

申请日：2023-08-04

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt

IPC分类号： G06F3/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

摘要： Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US12099454B2

公开(公告)日：2024-09-24

申请号：US17556376

申请日：2021-12-20

申请人： Rambus Inc.

发明人： Vlad Fruchter ,  Keith Lowery ,  George Michael Uhler ,  Steven Woo ,  Chi-Ming (Philip) Yeung ,  Ronald Lee

IPC分类号： G06F13/38 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/1668 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  Y02D10/00

摘要： System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

公开(公告)号：US12094565B2

公开(公告)日：2024-09-17

申请号：US17301089

申请日：2021-03-24

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely K. Tsern

IPC分类号： G06F12/00 ,  G11C7/10

CPC分类号： G11C7/1066 ,  G11C7/10 ,  G11C7/1072

摘要： A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

公开(公告)号：US12094553B2

公开(公告)日：2024-09-17

申请号：US17556363

申请日：2021-12-20

申请人： Rambus Inc.

发明人： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC分类号： G11C7/22 ,  G01R23/02 ,  G06F13/16 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  H03L1/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G11C7/04

CPC分类号： G11C29/50012 ,  G01R23/02 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03L1/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G11C7/04 ,  G11C2207/2254

摘要： The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US12093180B2

公开(公告)日：2024-09-17

申请号：US17853735

申请日：2022-06-29

申请人： Rambus Inc.

发明人： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC分类号： G06F12/0868 ,  G06F3/06

CPC分类号： G06F12/0868 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673

摘要： A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US12087681B2

公开(公告)日：2024-09-10

申请号：US18218280

申请日：2023-07-05

申请人： Rambus Inc.

发明人： Shahram Nikoukary ,  Jonghyun Cho ,  Nitin Juneja ,  Ming Li

IPC分类号： H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/49816

摘要： Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US12079486B2

公开(公告)日：2024-09-03

申请号：US18339812

申请日：2023-06-22

申请人： Rambus Inc.

发明人： Aws Shallal ,  Micheal Miller ,  Stephen Horn

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16 ,  G11C5/04 ,  G11C11/00 ,  G11C14/00 ,  G06F11/14 ,  G11C7/10

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F12/1441 ,  G06F13/1673 ,  G11C5/04 ,  G11C11/005 ,  G11C14/0009 ,  G06F11/14 ,  G06F13/1668 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C7/1051 ,  Y02D10/00

摘要： Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US12072817B2

公开(公告)日：2024-08-27

申请号：US18216439

申请日：2023-06-29

申请人： Rambus Inc.

发明人： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC分类号： G06F13/16

CPC分类号： G06F13/1668 ,  Y02D10/00

摘要： A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US20240283677A1

公开(公告)日：2024-08-22

申请号：US18590039

申请日：2024-02-28

申请人： Rambus Inc.

发明人： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC分类号： H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC分类号： H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

摘要： A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.