公开(公告)号：US20040216014A1

公开(公告)日：2004-10-28

申请号：US10853553

申请日：2004-05-25

发明人： Toshiyuki Okayasu ,  Masakatsu Suda

IPC分类号： G01R023/175 ,  H03K017/16 ,  H03K017/30 ,  G11B005/00 ,  G06K005/04 ,  G11B020/20

CPC分类号： H03K5/13 ,  G01R31/31922 ,  H03K5/133 ,  H03K5/14 ,  H03K2005/00071

摘要： To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being larger than the voltage Vss; an addition circuit that outputs to an output of the delay element, a predetermined voltage that is larger than the voltage Vss and smaller than the voltage Vdd. This delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. Furthermore, the addition circuit outputs a voltage substantially similar to a threshold voltage that said output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.

摘要翻译： 为了通过减小​​延迟装置的电源电压的变化来提高延迟装置的延迟时间的精度，以及延迟输入传输信号的延迟装置，包括：延迟元件，其对电源电压Vdd 和电源电压Vss，延迟发送信号，电压Vdd大于电压Vss; 输出到延迟元件的输出的加法电路，其大于电压Vss并小于电压Vdd的预定电压。 该延迟元件包括数字电路，输出与输入电压对应的两个可能值的输出电压之一。 此外，加法电路输出基本上类似于阈值电压的电压，数字电路的输出从两个可能值的输出电压之一反转到另一个的另一个。

公开(公告)号：US20040201402A1

公开(公告)日：2004-10-14

申请号：US10800192

申请日：2004-03-12

申请人： Rambus Inc.

发明人： Suresh Rajan ,  Scott Best

IPC分类号： H03K017/16

CPC分类号： H04L25/0278 ,  H04L25/0292

摘要： An input signal is transmitted from a first device to a second device. At the second device the input signal method is received, and an output signal is generated in response to the input signal. The output signal is sensed, and the input signal is dynamically terminated in response to sensing the output data. In some embodiments, the receiving, generating and dynamically terminating occur within a single integrated circuit. In some embodiments, the method includes detecting a signal voltage level of the input signal and causing a termination voltage level to change from a first voltage level to a second voltage level in response to the signal voltage level.

摘要翻译： 输入信号从第一设备发送到第二设备。 在第二装置处接收输入信号方法，并且响应于输入信号产生输出信号。 感测输出信号，响应感测输出数据，输入信号被动态地终止。 在一些实施例中，接收，产生和动态终止发生在单个集成电路内。 在一些实施例中，该方法包括检测输入信号的信号电压电平，并且响应于信号电压电平使终端电压电平从第一电压电平变为第二电压电平。

公开(公告)号：US20030169091A1

公开(公告)日：2003-09-11

申请号：US10147639

申请日：2002-05-17

发明人： Tom Youssef

IPC分类号： H03K017/16

CPC分类号： H01H9/167 ,  H03K17/18 ,  Y10T307/74 ,  Y10T307/766

摘要： A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

摘要翻译： 公开了用于检测诸如机械开关的开关的电路和方法，其具有耦合到两个或更多个电压源的第一端子，每个电压源提供表示逻辑高电平的不同电压电平。 该电路包括第一电路，其具有耦合到开关的输出，用于初始地在表示逻辑低电平的开关上放置第一电压。 电路还包括具有耦合到开关的输入的第二电路，用于感测跨越开关出现的电压差异，以及用于指示出现在开关两端的电压是否处于代表逻辑高电平的任何电压的输出，第二电路被控制 以基于第二电路的输出值来选择性地消除由电路吸取的静电流。

公开(公告)号：US20030141919A1

公开(公告)日：2003-07-31

申请号：US10059323

申请日：2002-01-31

发明人： Shoujun Wang ,  Tad Kwasniewski ,  Bill Bereza

IPC分类号： H03K017/16

CPC分类号： H03K17/04106

摘要： A circuit and methods for use in increasing both bandwidth and switching speed of CML circuits. Two differential pairs are provided with one differential pair having a size that is a fraction of the other pair. Thus, one pair will have a size of W while the other will have a size of W/A. Each one of the first differential pair is coupled to at least one of the second pair. By reconfiguring the connections between the two pairs, circuits which have fast charging/discharging times and increased bandwidth are obtained.

摘要翻译： 用于增加CML电路的带宽和开关速度的电路和方法。 两个差分对提供有一个差分对，其具有的尺寸是另一对的分数。 因此，一对将具有W的大小，而另一对将具有W / A的大小。 第一差分对中的每一个耦合到第二对中的至少一个。 通过重新配置两对之间的连接，获得具有快速充电/放电时间和增加的带宽的电路。

公开(公告)号：US20030122607A1

公开(公告)日：2003-07-03

申请号：US10318411

申请日：2002-12-13

申请人： Sanyo Electric Co., Ltd.

发明人： Nobuo Itoi

IPC分类号： H03K017/16

CPC分类号： H04N3/16 ,  H03F3/2171 ,  H03K7/08

摘要： A driving circuit of this invention has a comparator that compares an input signal with a sampling signal to perform a pulse width modulation to the input signal, a driving transistor circuit that switches according to an output signal of the comparator, and a filter that reduces a switching frequency component of the driving transistor circuit. The switching frequency of the driving transistor circuit is a product of multiplication of a horizontal frequency. Also, a PLL circuit that locks the frequency of the sampling signal to the frequency acquired from multiplication of the horizontal frequency is provided. Therefore, when the driving circuit with the PWM method is built in a television set, beat interference can be prevented, avoiding an unpleasant view caused by the raster interference on the television screen.

摘要翻译： 本发明的驱动电路具有将输入信号与采样信号进行比较以对输入信号进行脉宽调制的比较器，根据比较器的输出信号进行切换的驱动晶体管电路， 驱动晶体管电路的开关频率分量。 驱动晶体管电路的开关频率是水平频率相乘的乘积。 此外，提供了将采样信号的频率锁定到从水平频率的乘法获得的频率的PLL电路。 因此，当将具有PWM方式的驱动电路内置在电视机中时，可以防止拍频干扰，避免由电视屏幕上的光栅干扰引起的令人不快的视图。

公开(公告)号：US20030116810A1

公开(公告)日：2003-06-26

申请号：US10357841

申请日：2003-02-04

申请人： Samsung Electronics Co., Ltd.

发明人： Nam-Seog Kim ,  Uk-Rae Cho

IPC分类号： H03K017/16

CPC分类号： H03H21/0001 ,  H03H11/405

摘要： Disclosed is a programmable impedance control circuit, comprising a voltage divider, the voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance equal to N times said external resistance. The voltage divider outputs a second voltage. A reference voltage generator is provided for generating a third voltage corresponding to N/(NnullM) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (NnullM or NnullM).

公开(公告)号：US20030025548A1

公开(公告)日：2003-02-06

申请号：US10210605

申请日：2002-08-01

发明人： Seong-Jin Jang

IPC分类号： H03K017/16

CPC分类号： H02M3/073

摘要： A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.

摘要翻译： 电压产生电路通过在第一节点和第二节点之间共享电荷来在其输出节点处产生输出电压，以便将第二节点处的电位从第一电压增加到第二电压。 第一节点被充电到第三电压，并且第二节点被驱动到大于第三电压的第四电压。 电荷在第一节点和第二节点之间共享，使得第一和第二节点达到第三和第四电压之间的公共第五电压。 第一节点被驱动到大于第四电压的第六电压。 电荷在第一节点和输出节点之间共享，以在其上产生输出电压。

公开(公告)号：US20030020511A1

公开(公告)日：2003-01-30

申请号：US10029201

申请日：2001-12-28

申请人： Fujitsu Limited

发明人： Tendo Hirai ,  Atsushi Serizawa

IPC分类号： H03K017/16

CPC分类号： H05K1/0233 ,  H05K1/14

摘要： In an information processing apparatus, a transmission distortion of a signal transmitted between a module and a controller is reduced. A plurality of modules and a controller controlling the modules are mounted on a circuit board. A bus line connects the controller to the modules, the bus line including a main line and a plurality of branch lines each of which is branched from the main line and is connected to a respective one of the modules. Impedance matching elements are provided to the main line of the bus line so as to match a characteristic impedance between the controller and each of the modules. Each of the impedance matching elements is located behind a branch point of one of the branch lines connected to the respective one of the modules with respect to the controller.

摘要翻译： 在信息处理装置中，减少了在模块和控制器之间传输的信号的传输失真。 多个模块和控制模块的控制器安装在电路板上。 总线将控制器连接到模块，总线包括主线和多条分支线，每条支线从主线分支并连接到相应的一个模块。 将阻抗匹配元件提供给总线的主线，以便匹配控制器和每个模块之间的特性阻抗。 每个阻抗匹配元件位于相对于控制器连接到相应的一个模块的一条支线的分支点之后。

公开(公告)号：US20020084800A1

公开(公告)日：2002-07-04

申请号：US09750134

申请日：2000-12-29

发明人： Brent S. Crittenden ,  Andrew M. Volk ,  Timothy J. Maloney

IPC分类号： H03K017/16

CPC分类号： H04L25/028 ,  H03K17/167 ,  H04L25/0278

摘要： The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

摘要翻译： 驱动驱动传输线另一端的负载的驱动器的阻抗被动态地改变，以提高转换速率和毛刺终止。 驱动器在边沿转换的初始部分被控制为具有低阻抗，从而提供当时所需的强大驱动力。 在边缘转换中的第一预定位置，大致等于飞行时间，驱动器阻抗升高到大致等于传输线阻抗的值，以有效地终止任何反射信号。

公开(公告)号：US20020050838A1

公开(公告)日：2002-05-02

申请号：US09853101

申请日：2001-05-10

申请人： Samsung Electronics Co., Ltd.

发明人： Nam-Seog Kim ,  Uk-Rae Cho

IPC分类号： H03K017/16

CPC分类号： H03K19/0005

摘要： A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.