公开(公告)号：US5832533A

公开(公告)日：1998-11-03

申请号：US687825

申请日：1996-07-26

Applicant: Ramesh Chandra Agarwal ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

Inventor： Ramesh Chandra Agarwal ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F9/355 ,  G06F9/3013 ,  G06F9/30138

Abstract: In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.

Abstract translation: 在具有多个通用寄存器的数据处理单元中，加载指令。 这样的指令包括操作和至少一个操作数字段，其中操作数字段指定多个基本寄存器中的一个和位移值。 为了计算由这样一个操作数字段指定的通用寄存器地址，位移值被添加到存储在由一部分操作数字段指定的基址寄存器中的基础值。 最后，数据处理单元利用所计算的通用寄存器地址来寻址所选择的一个通用寄存器，以执行指定的操作。 因此，数据处理单元能够寻址比可以使用由操作数字段内的有限数目的位表示的值直接寻址的更大数量的通用寄存器。

公开(公告)号：US07487169B2

公开(公告)日：2009-02-03

申请号：US10904732

申请日：2004-11-24

Applicant: Ramesh Chandra Agarwal

Inventor： Ramesh Chandra Agarwal

IPC: G06F7/00 ,  G06F17/00 ,  G06F12/00 ,  G06F17/30

CPC classification number: H03M7/3084 ,  H03M7/30 ,  Y10S707/99942 ,  Y10S707/99953

Abstract: A differential compression method and computer program product combines hash value techniques and suffix array techniques. The invention finds the best matches for every offset of the version file, with respect to a certain granularity and above a certain length threshold. The invention has two variations depending on block size choice. If the block size is kept fixed, the compression performance of the invention is similar to that of the greedy algorithm, without the expensive space and time requirements. If the block size is varied linearly with the reference file size, the invention can run in linear-time and constant-space. It has been shown empirically that the invention performs better than certain known differential compression algorithms in terms of compression and speed.

Abstract translation: 差分压缩方法和计算机程序产品组合了哈希值技术和后缀阵列技术。 本发明针对某个粒度并高于一定长度的阈值，找到版本文件的每个偏移的最佳匹配。 根据块大小的选择，本发明具有两种变化。 如果块大小保持固定，则本发明的压缩性能与贪心算法相似，没有昂贵的空间和时间要求。 如果块大小与参考文件大小线性变化，则本发明可以在线性时间和恒定空间中运行。 从经验可以看出，本发明在压缩和速度方面表现优于某些已知的差分压缩算法。

公开(公告)号：US5752072A

公开(公告)日：1998-05-12

申请号：US644753

申请日：1996-05-09

Applicant: Ramesh Chandra Agarwal

Inventor： Ramesh Chandra Agarwal

IPC: G06F7/24 ,  G06F7/08 ,  G06F7/42

CPC classification number: G06F7/24

Abstract: A sorting scheme which does not require any compare or branch instructions is particularly useful for computers with multiple parallel functional units. Sorting two numbers or binary strings is performed using arithmetic instructions instead of conventional compare and branch instructions, thereby improving the performance of superscalar and very large instruction word (VLIW) computers. When applied to reduced instruction set computers (RISC), the sorting scheme provides better utilization of floating-point units. The sorting scheme allows floating point representation of data and floating-point instructions to sort binary strings.

Abstract translation: 不需要任何比较或分支指令的排序方案对于具有多个并行功能单元的计算机特别有用。 使用算术指令而不是传统的比较和分支指令对两个数字或二进制串进行排序，从而提高超标量和非常大的指令字（VLIW）计算机的性能。 当应用于精简指令集计算机（RISC）时，排序方案可以更好地利用浮点数据。 排序方案允许数据的浮点表示和浮点指令对二进制字符串进行排序。

公开(公告)号：US5751619A

公开(公告)日：1998-05-12

申请号：US589770

申请日：1996-01-22

Applicant: Ramesh Chandra Agarwal ,  Bruce Martin Fleischer ,  Fred Gehrung Gustavson

Inventor： Ramesh Chandra Agarwal ,  Bruce Martin Fleischer ,  Fred Gehrung Gustavson

IPC: G06F7/52 ,  G06F7/38

CPC classification number: G06F7/5312

Abstract: An arithmetic unit keeps a result in carry-save form and uses this form of the result as an input to the next iteration in recurrent computations. The full adder in the recurrent path is eliminated by implementing multiplication by Y(i), where Y(i) is available only in carry-save form. The carry-save arithmetic unit generates a plurality of partial products whose sum is the product AXB, where A is one binary input and B is either a second binary input B' or the sum C'+S' of two binary inputs C' and S'. A selection is made as to whether B is equal to B' or C'+S'. The plurality of partial products and an addition input Z are compressed to two partial products C and S whose sum C+S equals the sum of the plurality of partial products and Z. The partial products C and S are added to produce a binary result X equal to A.times.B+Z. The full adder in the recurrent path is eliminated by a feedback path which returns the partial products C and S to the inputs C' and S' for a next iteration.

Abstract translation: 算术单元将结果保存在进位保存格式中，并将此结果形式作为反复计算中下一次迭代的输入。 通过实现乘以Y（i），消除了循环路径中的全加器，其中Y（i）仅以进位保存形式可用。 进位保存算术单元产生多个部分乘积，它们的和是乘积AXB，其中A是一个二进制输入，B是二进制输入B'或两个二进制输入C'的和C'+ S' S'。 选择B是否等于B'或C'+ S'。 多个部分乘积和加法输入Z被压缩成两个部分乘积C和S，它们的和C + S等于多个部分乘积和Z的和。加上部分乘积C和S以产生二进制结果X 等于AxB + Z。 反馈路径中的全加器由反馈路径消除，该反馈路径将部分乘积C和S返回到输入C'和S'进行下一次迭代。

公开(公告)号：US5680338A

公开(公告)日：1997-10-21

申请号：US368172

申请日：1995-01-04

Applicant: Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson ,  James B. Shearer

Inventor： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson ,  James B. Shearer

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.

Abstract translation: 在使用包括多个元素的向量的一部分来处理向量计算的向量处理系统中，提供了用于接收向量和向量处理命令的装置。 矢量处理系统还包括用于接收和存储起始元素值和终止元素值的装置。 算术逻辑单元耦合到用于接收向量的装置，用于接收向量处理命令的装置和用于接收起始元素和终止元素值的装置。 算术逻辑单元还包括仅利用向量中的一个或多个元素来执行向量处理命令的装置，其由起始元素值和终止元素值选择。

公开(公告)号：US5890222A

公开(公告)日：1999-03-30

申请号：US368176

申请日：1995-01-04

Applicant: Ramesh Chandra Agarwal ,  John Joseph Haddow Forrest ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

Inventor： Ramesh Chandra Agarwal ,  John Joseph Haddow Forrest ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F12/00

CPC classification number: G06F9/34 ,  G06F9/30098 ,  G06F9/35

Abstract: In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.

Abstract translation: 在数据处理单元中，加载指令。 这样的指令包括用于存储操作码和至少一个操作数字段的操作码字段，其中操作数字段包括用于指示启用间接寻址模式的间接寻址模式指示符。 如果启用间接寻址模式，则从间接寄存器的地址字段中选择通用寄存器地址。 最后，在数据处理单元执行操作码期间，数据处理单元利用通用寄存器地址来寻址多个通用寄存器中的选定一个。

公开(公告)号：US5887183A

公开(公告)日：1999-03-23

申请号：US368173

申请日：1995-01-04

Applicant: Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Terry L. Lyon ,  Brett Olsson ,  James B. Shearer

Inventor： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Terry L. Lyon ,  Brett Olsson ,  James B. Shearer

IPC: G06F9/312 ,  G06F15/80

CPC classification number: G06F9/30043 ,  G06F15/8092 ,  G06F9/30036

Abstract: A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Abstract translation: 具有多个元素的向量存储在输入存储区域中，其中矢量元素以第一模式存储。 此后，元件以第一顺序从输入存储区域传送到向量寄存器接口单元。 从矢量寄存器接口单元，将元件传送到输出存储区域，并以多个预选图案之一存储在可寻址位置。 输入存储区域可以由高速缓冲存储器或寄存器阵列来实现。 输出存储区域可以用高速缓冲存储器或寄存器阵列来实现。 输入存储区域中的第一图案可以包括交替的实数和虚部元素。 多个预选图案可以包括相反的顺序图案，或者将实数元素和虚构元素分离成两个向量寄存器。

公开(公告)号：US5825677A

公开(公告)日：1998-10-20

申请号：US619456

申请日：1996-03-20

Applicant: Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred Gehrung Gustavson ,  Mark Alan Johnson ,  Brett Olsson

Inventor： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred Gehrung Gustavson ,  Mark Alan Johnson ,  Brett Olsson

IPC: G06F17/16 ,  G06F15/80

CPC classification number: G06F15/8092 ,  G06F15/8023

Abstract: A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.

Abstract translation: 描述了允许高速数值计算的矩阵处理单元。 处理单元是由多个处理元件形成的矢量处理单元。 第I处理单元具有一组N个寄存器，其中存储了N个数据向量的第I个元素或单词。 每个处理元件具有能够对N个寄存器组中的N个元素执行算术运算的算术单元。 每个数据矢量都有K个元素。 因此，有K个处理元素。 矩阵处理单元的向量运算同时对两个向量的全部要素进行相同的运算。 可以在先前的矢量操作之后的一个机器周期内执行随后的矢量操作。

公开(公告)号：US5770894A

公开(公告)日：1998-06-23

申请号：US678008

申请日：1996-07-10

Applicant: Ramesh Chandra Agarwal

Inventor： Ramesh Chandra Agarwal

IPC: G06F9/38 ,  G06F9/45

CPC classification number: G06F9/3842

Abstract: A computer implemented method performed by a processor having multiple functional units avoids branches in decision support codes by doing arithmetic instructions incorporating condition codes generated by compare instructions. The method comprising the steps of analyzing operations in code to be performed by said processors to identify branch operations, substituting for identified branch operations arithmetic condition codes, decoding and dispatching multiple instructions in one processor cycle, and executing multiple functions in parallel per cycle using each of the functional units of said processor.

Abstract translation: 由具有多个功能单元的处理器执行的由计算机实现的方法通过执行包含由比较指令生成的条件码的算术指令来避免决策支持代码中的分支。 该方法包括以下步骤：分析由所述处理器执行的代码中的操作以识别分支操作，代替所识别的分支操作算术条件代码，在一个处理器周期中对多个指令进行解码和调度，以及每个周期使用每个周期并行执行多个功能 的处理器的功能单元。

公开(公告)号：US5758176A

公开(公告)日：1998-05-26

申请号：US313970

申请日：1994-09-28

Applicant: Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred Gehrung Gustavson ,  Mark Alan Johnson ,  Brett Olsson

Inventor： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred Gehrung Gustavson ,  Mark Alan Johnson ,  Brett Olsson

IPC: G06F9/302 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/3001 ,  G06F15/8007 ,  G06F15/8092 ,  G06F9/3885 ,  G06F9/3887

Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

Abstract translation: 提供了与超标量数据处理系统结合使用的单指令多数据（SIMD）执行单元。 SIMD执行单元耦合到超标量处理器内的分支执行单元。 分支执行单元从存储器取出指令，并通过指令总线向SIMD执行单元分派向量处理指令。 SIMD执行单元包括用于执行算术运算的控制单元和多个处理元件。 处理元件还包括具有多个寄存器的寄存器文件和耦合到寄存器文件的算术逻辑单元。 算术逻辑单元可以包括用于执行定点矢量计算的定点单元和用于执行浮点矢量计算的浮点单元。 一旦SIMD执行单元中的控制单元接收到向量指令，则控制单元将该指令转换为SIMD执行单元内的选定处理元件执行的命令。 如果这样的向量指令需要访问存储器，则可以利用超标量处理器内的固定点执行单元来计算存储器地址，然后SIMD执行单元利用存储器地址访问存储器。