-
公开(公告)号：US20100083195A1
公开(公告)日：2010-04-01
申请号：US12243768
申请日：2008-10-01
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.
摘要翻译： 公开了一种复制控制信号源的方法，包括：接收功能块的描述，该功能块包括多个多路复用器结构，多个存储块和至少一个复用器结构的组合中的至少一个，并且至少 一个记忆块 识别控制所述多个多路复用器结构，所述多个存储器块中的至少一个以及至少一个复用器结构和至少一个存储器块的所述组合的控制信号; 并且，确定第一副本控制信号和第二复制控制信号，所述第一副本控制信号和所述第二副本控制信号共同起到所述控制信号的作用，以控制所述多个多路复用器结构中的至少一个，所述多个存储器 块，以及所述至少一个复用器结构和至少一个存储器块的组合。
-
公开(公告)号：US08001497B2
公开(公告)日：2011-08-16
申请号：US12243768
申请日：2008-10-01
CPC分类号： G06F17/505 , G06F2217/84
摘要： Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.
摘要翻译： 公开了一种复制控制信号源的方法，包括：接收功能块的描述，该功能块包括多个多路复用器结构，多个存储块和至少一个复用器结构的组合中的至少一个，并且至少 一个记忆块 识别控制所述多个多路复用器结构，所述多个存储器块中的至少一个以及至少一个复用器结构和至少一个存储器块的所述组合的控制信号; 并且，确定第一副本控制信号和第二复制控制信号，所述第一副本控制信号和所述第二副本控制信号共同起到所述控制信号的作用，以控制所述多个多路复用器结构中的至少一个，所述多个存储器 块，以及所述至少一个复用器结构和至少一个存储器块的组合。
-
公开(公告)号：US07082584B2
公开(公告)日：2006-07-25
申请号：US10427609
申请日：2003-04-30
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
摘要翻译： 一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。 选择了一种集成电路设计供应商的设计规则的RTL平台。 设计规则从图形用户界面的RTL平台显示。 从图形用户界面中选择了多个设计规则。 在RTL代码的RTL平台中对每个选定的设计规则进行分析。 生成分析结果作为每个选定设计规则的输出。
-
公开(公告)号：US20100217564A1
公开(公告)日：2010-08-26
申请号：US12393358
申请日：2009-02-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A method of physical simulation of an integrated circuit design comprising the steps of (A) reading design information for an integrated circuit from a computer readable storage medium, (B) reading library information and physical design information from the computer readable storage medium, (C) simulating the integrated circuit design based upon the library information and the physical design information using a computer, where the simulation of the integrated circuit design provides signoff accurate results and (D) determining whether the integrated circuit design meets one or more performance goals based upon results of the simulation of the integrated circuit design.
摘要翻译： 一种集成电路设计的物理模拟方法，包括以下步骤：（A）从计算机可读存储介质读取集成电路的设计信息，（B）从计算机可读存储介质读取库信息和物理设计信息，（C ）基于库信息和使用计算机的物理设计信息来模拟集成电路设计，其中集成电路设计的仿真提供了签约准确的结果，以及（D）确定集成电路设计是否满足一个或多个基于 集成电路设计仿真结果。
-
5.发明申请Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database 审中-公开用于分析集成电路设计的方法和计算机程序，以使用设计闭包知识库和物理设计数据库来识别和解决以多规则违规为特征的有问题的结构公开(公告)号：US20070079266A1
公开(公告)日：2007-04-05
申请号：US11241033
申请日：2005-09-30
申请人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
发明人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.
摘要翻译： 一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。 在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的 集成电路设计中的每个设计规则违规的主要和次要对象列表。 每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略 违反设计关闭指引报告。
-
公开(公告)号：US20090282307A1
公开(公告)日：2009-11-12
申请号：US12117381
申请日：2008-05-08
CPC分类号： G01R31/31835 , G01R31/318314
摘要： A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.
摘要翻译： 公开了一种优化测试代码生成的方法。 该方法通常包括以下步骤：（A）从数据库（i）读取多个断言，（ii）测试台和（iii）所有被测设计的目标代码覆盖，（B）一起生成（i） 多个第一测试向量来测试断言，以及（ii）可应用于测试台的多个第二测试向量，（C）识别第一测试向量与第二测试向量之间的一个或多个冗余测试向量集，以及（D） 生成测试代码以使用第一测试向量和第二测试向量的子集在测试台上测试被测设计，该子集包括冗余测试向量集的单个实例。
-
公开(公告)号：US20090063564A1
公开(公告)日：2009-03-05
申请号：US11849391
申请日：2007-09-04
IPC分类号： G06F17/30
CPC分类号： G06F17/5022 , G06F2217/10
摘要： A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.
摘要翻译： 公开了统计设计关闭的方法。 该方法通常包括以下步骤：（A）从数据库读取统计数据，统计数据定义多个芯片产量改进，分别在多个设计闭合类别中的每一个中的芯片产量改进之一，芯片产量改进 （B）基于统计数据计算当前设计关闭项目的多个目标，分别在每个设计关闭类别中的目标之一和（C）生成一个 向用户显示指示预期用于当前设计关闭项目的多个资源的资源报告。
-
公开(公告)号：US07895546B2
公开(公告)日：2011-02-22
申请号：US11849391
申请日：2007-09-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/10
摘要： A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.
摘要翻译： 公开了统计设计关闭的方法。 该方法通常包括以下步骤：（A）从数据库读取统计数据，统计数据定义多个芯片产量改进，分别在多个设计闭合类别中的每一个中的芯片产量改进之一，芯片产量改进 （B）基于统计数据计算当前设计关闭项目的多个目标，分别在每个设计关闭类别中的目标之一和（C）生成一个 向用户显示指示预期用于当前设计关闭项目的多个资源的资源报告。
-
公开(公告)号：US07844929B2
公开(公告)日：2010-11-30
申请号：US12117381
申请日：2008-05-08
IPC分类号： G06F17/50
CPC分类号： G01R31/31835 , G01R31/318314
摘要： A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.
摘要翻译： 公开了一种优化测试代码生成的方法。 该方法通常包括以下步骤：（A）从数据库（i）读取多个断言，（ii）测试台和（iii）所有被测设计的目标代码覆盖，（B）一起生成（i） 多个第一测试向量来测试断言，以及（ii）可应用于测试台的多个第二测试向量，（C）识别第一测试向量与第二测试向量之间的一个或多个冗余测试向量集，以及（D） 生成测试代码以使用第一测试向量和第二测试向量的子集在测试台上测试被测设计，该子集包括冗余测试向量集的单个实例。
-
公开(公告)号：US07086015B2
公开(公告)日：2006-08-01
申请号：US10844664
申请日：2004-05-12
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.
摘要翻译： 公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括以下步骤：（a）作为输入接收用于集成电路设计的第一寄存器传送级代码; （b）接收用户定义的最佳多路复用结构作为输入; （c）分析第一寄存器传送级代码以识别关键的多路复用结构; （d）将全局多路复用结构划分为与用户定义的最佳多路复用结构相同的本地多路复用结构; 以及（e）为所述集成电路设计产生用本地多路复用结构代替所述全局多路复用结构的第二寄存器传送级代码作为输出。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.02 秒)
