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公开(公告)号：US20100268880A1
公开(公告)日：2010-10-21
申请号：US12424348
申请日：2009-04-15
CPC分类号： G06F12/0886 , G06F9/30047 , G06F9/345
摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.
摘要翻译： 公开了一种用于操作缓存系统的方法，系统和计算机程序产品。 高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。 在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。 当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。 可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。
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公开(公告)号：US07783842B2
公开(公告)日：2010-08-24
申请号：US10339764
申请日：2003-01-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I/O communication by the I/O communication adapter and, in response to snooping the I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.
摘要翻译： 处理单元包括处理器核心，耦合到处理器核心的输入/输出（I / O）通信适配器以及耦合到处理器核心和I / O通信适配器的高速缓存系统。 缓存系统包括缓存阵列，缓存目录和高速缓存控制器。 缓存控制器通过I / O通信适配器监听I / O通信，并且响应于窥探I / O通信适配器以独占状态执行输出数据的I / O数据写入，使存储在高速缓存阵列中的对应数据无效 。
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3.发明申请Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States 失效通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制公开(公告)号：US20090157945A1
公开(公告)日：2009-06-18
申请号：US12352462
申请日：2009-01-12
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。
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公开(公告)号：US07117319B2
公开(公告)日：2006-10-03
申请号：US10313321
申请日：2002-12-05
IPC分类号： G06F12/00
CPC分类号： G06F9/462 , G01R31/318536 , G06F9/30101 , G06F9/30116 , G06F9/3012 , G06F9/3013
摘要： A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.
摘要翻译： 公开了一种用于管理对于在处理器中执行处理至关重要的处理器的硬结构状态的方法和系统。 当处理器接收到中断时，硬设计状态的卷影副本从处理器存储到存储器。 硬架构的卷影副本允许快速保存中断过程的硬结构状态，从而可以将下一个进程的架构状态立即存储在处理器中。
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5.发明授权Acceleration of input/output (I/O) communication through improved address translation 失效通过改进地址转换来加速输入/输出（I / O）通信公开(公告)号：US06976148B2
公开(公告)日：2005-12-13
申请号：US10339766
申请日：2003-01-09
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081
摘要： An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.
摘要翻译： I / O通信适配器从处理器核心接收参考在处理器核心的有效地址空间内识别存储位置的有效地址的I / O命令。 响应于I / O命令的接收，I / O通信适配器通过参考翻译数据结构将有效地址转换成实地址。 然后，I / O通信适配器使用实际地址访问存储位置，以执行由I / O命令指定的I / O数据传输。
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6.发明授权Partitioned cache and management method for selectively caching data by type 有权用于按类型选择性缓存数据的分区缓存和管理方法公开(公告)号：US06421761B1
公开(公告)日：2002-07-16
申请号：US09435950
申请日：1999-11-09
IPC分类号： G06F1200
CPC分类号： G06F12/0848
摘要： A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.
摘要翻译： 用于按类型选择性地缓存数据的分区高速缓存和管理方法通过划分一致类集合来存储特定数据类型（例如操作系统例程和这些例程所使用的数据）来提高高速缓冲存储器的效率。 通过将相关应用程序的值放置在缓存中的不同分区中，可以在缓存中保持同时可用的值，而不会造成任何干扰，从而导致某些值的释放，从而有利于新加载的值。 另外，可以执行将来自不相关的应用程序的数据放在同一分区中，以允许高速缓存翻转不同时间的值。
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7.发明授权High performance multiprocessor system with exclusive-deallocate cache state 失效具有独占解除缓存状态的高性能多处理器系统公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译： 高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中 与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。 如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。 相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值 的计算机系统。 如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。
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8.发明授权Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制公开(公告)号：US07493478B2
公开(公告)日：2009-02-17
申请号：US10313308
申请日：2002-12-05
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。
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公开(公告)号：US06983347B2
公开(公告)日：2006-01-03
申请号：US10313319
申请日：2002-12-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0831
摘要： A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.
摘要翻译： 公开了一种用于管理存储的软状态信息的方法和系统，诸如高速缓冲存储器的内容和对执行处理器内的处理非关键的地址转换信息。 空闲进程的软状态存储在虚拟高速缓存中的系统内存中。 通过对系统内存中的虚拟缓存进行侦听kill类型操作来维护软状态的缓存一致性。
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10.发明授权Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention 失效缓存一致性协议，其中使用加载指令提示位来指示由干预提供的修改的高速缓存行的释放公开(公告)号：US06374333B1
公开(公告)日：2002-04-16
申请号：US09437176
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译： 一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。
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