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公开(公告)号：US10049052B2
公开(公告)日：2018-08-14
申请号：US14524378
申请日：2014-10-27
IPC分类号： G06F12/08 , G06F12/0897 , G06F12/0804
摘要： A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.
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公开(公告)号：US09826252B2
公开(公告)日：2017-11-21
申请号：US14445718
申请日：2014-07-29
IPC分类号： H04N19/89
CPC分类号： H04N19/89
摘要： A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.
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公开(公告)号：US10540284B2
公开(公告)日：2020-01-21
申请号：US14445237
申请日：2014-07-29
IPC分类号： G06F12/0831 , G06F12/14 , G06F12/084 , G06F12/0811
摘要： A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
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4.发明授权Fault tolerance of data processing steps operating in either a parallel operation mode or a non-synchronous redundant operation mode 有权以并行操作模式或非同步冗余操作模式运行的数据处理步骤的容错公开(公告)号：US09052887B2
公开(公告)日：2015-06-09
申请号：US13577072
申请日：2010-02-16
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.
摘要翻译： 一种在包括至少两个数据处理单元的数据处理器中处理数据的方法。 该方法包括在并行操作期间同时在数据处理单元中执行不同的数据处理步骤，以及在非同步冗余操作期间在数据处理单元中复制所选择的相同数据处理步骤的性能。 非同步冗余操作包括在数据处理单元之一中所选择的相同数据处理步骤的初始性能以及优先于另一个数据处理单元中的初始性能开始的数据处理步骤的复制性能。 记录表示来自初始性能的结果的初始结果数据，并与代表复制性能的结果的复制结果数据进行比较，并且在差异的情况下产生错误信号。
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公开(公告)号：US20160124800A1
公开(公告)日：2016-05-05
申请号：US14889476
申请日：2013-05-13
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0721 , G06F11/076 , G06F11/079
摘要： A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.
摘要翻译： 描述具有功能状态，复位状态和一个或多个可断言故障源的微控制器单元（MCU）。 每个故障源都有自己的故障源断言计数和自己的故障源断言限制; MCU被布置为以循环方式执行以下操作序列：如果一个或多个故障源被断言，则从功能状态传递到复位状态，并且将相应的故障源断言计数增加一个增量; 如果一个或多个故障源断言计数超过相应的故障源断言限制，则禁用相应的故障源; 并从复位状态转移到功能状态。 还公开了一种操作MCU的方法。
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公开(公告)号：US09823959B2
公开(公告)日：2017-11-21
申请号：US14889476
申请日：2013-05-13
CPC分类号： G06F11/0793 , G06F11/0721 , G06F11/076 , G06F11/079
摘要： A microcontroller unit having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.
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7.发明申请DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR 有权数据处理方法，数据处理器和包括数据处理器的设备公开(公告)号：US20120304024A1
公开(公告)日：2012-11-29
申请号：US13577072
申请日：2010-02-16
IPC分类号： G06F11/07
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.
摘要翻译： 一种在包括至少两个数据处理单元的数据处理器中处理数据的方法。 该方法包括在并行操作期间同时在数据处理单元中执行不同的数据处理步骤，以及在非同步冗余操作期间在数据处理单元中复制所选择的相同数据处理步骤的性能。 非同步冗余操作包括在数据处理单元之一中所选择的相同数据处理步骤的初始性能以及优先于另一个数据处理单元中的初始性能开始的数据处理步骤的复制性能。 记录表示来自初始性能的结果的初始结果数据，并与代表复制性能的结果的复制结果数据进行比较，并且在差异的情况下产生错误信号。
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