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公开(公告)号：US09350529B1
公开(公告)日：2016-05-24
申请号：US14665144
申请日：2015-03-23
CPC分类号： H04L7/033 , H04L25/0278 , H04L25/4923
摘要： A logical transmission system includes a driver configured to receive a source data and output a first voltage at a first node; a transmission line of a characteristic impedance configured to couple the first node to a second node; a three-point three-level slicer configured to receive a second voltage at the second node and output a first ternary signal, a second ternary signal, and a third ternary in accordance with a first reference voltage, a second reference voltage, a first clock, a second clock, and a third clock; and a CDR (clock-data recovery) unit configured to receive a reference clock, the first ternary signal, the second ternary signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage, the first clock, the second clock, and the third clock.
摘要翻译： 逻辑传输系统包括被配置为接收源数据并在第一节点输出第一电压的驱动器; 特征阻抗的传输线，被配置为将所述第一节点耦合到第二节点; 配置为在第二节点处接收第二电压并根据第一参考电压，第二参考电压，第一时钟和第二时钟输出第一三进制信号，第二三进制信号和第三三进制信号的三点三电平限幅器 ，第二时钟和第三时钟; 以及CDR（时钟数据恢复）单元，被配置为接收参考时钟，所述第一三进制信号，所述第二三进制信号和所述第三三进制信号，并输出恢复的数据，所述第一参考电压，所述第二参考电压， 时钟，第二个时钟和第三个时钟。
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公开(公告)号：US08648640B1
公开(公告)日：2014-02-11
申请号：US13656771
申请日：2012-10-22
IPC分类号： H03K3/00
摘要： Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.
摘要翻译： 提供了用于提取电路的装置和方法。 在一种配置中，一种装置包括：边缘提取电路，用于接收第一时钟信号并输出第二时钟信号，其中第二时钟的占空比基本上小于第一时钟的占空比; 晶体管，用于接收第二时钟信号并输出电流信号; 传输线，用于在第一端接收当前信号并将该当前信号传送到第二端; 终端电路，用于在第二端接收电流信号，并将电流信号转换为电压信号; 以及边缘检测电路，用于通过检测电压信号的边缘来输出第三时钟。 在一个实施例中，边缘检测电路包括逆变器。 在另一个实施例中，边缘检测电路包括比较器。
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3.发明申请公开(公告)号：US20160269029A1
公开(公告)日：2016-09-15
申请号：US14642887
申请日：2015-03-10
IPC分类号： H03K19/0185 , H03K19/094
CPC分类号： H03K19/018557 , H03K19/09429
摘要： In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit in accordance with the logical signal; controlling an output impedance of the driver circuit using a finite state machine (FSM); transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load circuit comprising a data detector.
摘要翻译： 在一个实施例中，一种方法包括接收逻辑信号; 使用根据逻辑信号的驱动电路在第一电路节点处驱动源极电压; 使用有限状态机（FSM）控制驱动器电路的输出阻抗; 经由传输线将源电压传输到第二电路节点; 以及用包括数据检测器的负载电路终接第二电路节点。
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公开(公告)号：US20160268891A1
公开(公告)日：2016-09-15
申请号：US14641474
申请日：2015-03-09
IPC分类号： H02M3/07 , H03K3/017 , H03K5/1534 , H03K19/003 , H03K19/20
CPC分类号： H02M3/07 , H03K5/1534 , H03K19/00346 , H03K19/20
摘要： In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit; generating an impulsive edge signal by detecting a transition of the logical signal; converting the impulsive edge signal into an impulsive charge pump current using a charge pump circuit; injecting the impulsive charge pump current into the first circuit node; transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load.
摘要翻译： 在一个实施例中，一种方法包括接收逻辑信号; 使用驱动电路在第一电路节点处驱动源极电压; 通过检测逻辑信号的转换来产生脉冲边缘信号; 使用电荷泵电路将脉冲边缘信号转换成脉冲电荷泵电流; 将脉冲电荷泵电流注入到第一电路节点中; 经由传输线将源电压传输到第二电路节点; 并以负载终止第二电路节点。
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