-
公开(公告)号：US07516424B2
公开(公告)日：2009-04-07
申请号：US11358456
申请日：2006-02-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.
摘要翻译： 公开了一种用于建模和模拟集成电路的功率分级元件的方法，系统和计算机程序产品。 在对功率宏进行建模时，本发明不将所有逻辑门或元件建模为功率门限，相反，本发明仅将连接到集成开关的锁存器模拟为被加电的宏。 另外，附加到电力宏观的栅栏电路被建模为包括额外的控制信号，以将强力宏观的电力状态强制进入栅栏电路。
-
2.发明申请Register file cell with soft error detection and circuits and methods using the cell 失效使用软件错误检测注册文件单元，使用单元格的电路和方法公开(公告)号：US20070300131A1
公开(公告)日：2007-12-27
申请号：US11446348
申请日：2006-06-02
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C29/32 , G11C2029/3202
摘要： Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.
摘要翻译： 为包括被配置为存储第一值的主存储部分和耦合到主存储部分的辅助存储部分的寄存器文件单元提供技术。 次存储部分被配置为在测试操作期间用作扫描锁存器，并且还被配置为在正常操作期间存储第二值。 第二个值是第一个值的副本。 小区还包括错误检测部分，其耦合到主存储部分和辅助存储部分，并且被配置为指示由软错误引起的第一值和第二值之间的差异。
-
公开(公告)号：US06876252B2
公开(公告)日：2005-04-05
申请号：US10609360
申请日：2003-06-28
CPC分类号： H03K17/163 , H03K17/164
摘要： A semiconductor integrated circuit including a non-abrupt switching mechanism for a sleep transistor of a power gate structure to reduce ground bounce is provided. The semiconductor integrated circuit comprises a supply voltage line; a ground voltage line; a virtual ground voltage line; a logic circuit coupled to the supply voltage line and the virtual ground voltage line; at least one sleep transistor for controlling current flow to the logic circuit, the sleep transistor being coupled to the virtual ground voltage line and the ground voltage line; and a non-abrupt switching circuit for sequentially controlling the sleep transistor. The switching mechanism reduces the magnitude of voltage glitches on the power and ground rails as well as the minimum time required to stabilize power and ground.
摘要翻译： 提供一种包括用于减少地面反弹的功率门结构的休眠晶体管的非突变切换机构的半导体集成电路。 半导体集成电路包括电源电压线; 地电压线; 虚拟地电压线; 耦合到电源电压线和虚拟接地电压线的逻辑电路; 至少一个睡眠晶体管，用于控制到逻辑电路的电流，睡眠晶体管耦合到虚拟接地电压线和地电压线; 以及用于依次控制睡眠晶体管的非突变切换电路。 开关机构可以减少电源和接地导轨上的电压毛刺的大小以及稳定电源和接地所需的最短时间。
-
公开(公告)号：US06977519B2
公开(公告)日：2005-12-20
申请号：US10437764
申请日：2003-05-14
CPC分类号： H03K19/0016
摘要： A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.
摘要翻译： 提供了功率门结构和相应的方法，用于控制用于多个模式的逻辑电路的接地连接，其中功率栅极结构包括NFET晶体管，与NFET晶体管信号通信的PFET晶体管，源极和漏极 分别与晶体管的漏极信号通信的接地节点和与晶体管的源极信号通信的接地轨道; 并且相应的方法包括在第一或活动模式下将逻辑电路与接地连接解耦，在第二或状态保持模式下将逻辑电路保持在接地连接以上的阈值电压处，并且切断逻辑电流之间的电流 电路和接地连接处于第三或非状态保持模式。
-
公开(公告)号：US07138825B2
公开(公告)日：2006-11-21
申请号：US10880111
申请日：2004-06-29
IPC分类号： H03K17/16
CPC分类号： H03K19/0019
摘要： A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.
-
6.发明授权Register file cell with soft error detection and circuits and methods using the cell 失效使用软件错误检测注册文件单元，使用单元格的电路和方法公开(公告)号：US07562273B2
公开(公告)日：2009-07-14
申请号：US11446348
申请日：2006-06-02
IPC分类号： G01R31/28
CPC分类号： G11C29/52 , G11C29/32 , G11C2029/3202
摘要： Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.
摘要翻译： 为包括被配置为存储第一值的主存储部分和耦合到主存储部分的辅助存储部分的寄存器文件单元提供技术。 次存储部分被配置为在测试操作期间用作扫描锁存器，并且还被配置为在正常操作期间存储第二值。 第二个值是第一个值的副本。 小区还包括错误检测部分，其耦合到主存储部分和辅助存储部分，并且被配置为指示由软错误引起的第一值和第二值之间的差异。
-
公开(公告)号：US07486108B2
公开(公告)日：2009-02-03
申请号：US11518078
申请日：2006-09-08
IPC分类号： H03K17/16
CPC分类号： H03K19/0019
摘要： A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.
摘要翻译： 提供电荷回收功率门和相应的方法，用于使用功能单元的电容性负载与电荷回收装置的寄生电容之间的电荷共享效应，以接通虚拟地面和地面之间的开关装置，电荷回收 功率门，包括第一晶体管，与第一晶体管的第一端子进行信号通信的虚拟地，与第一晶体管的第二端子进行信号通信的地，电容器，具有与第三晶体管的第三端子信号通信的第一端子 第一晶体管和与地面信号通信的第二端子，以及第二晶体管，其具有与虚拟接地信号通信的第一端子和与第一晶体管的第三端子信号通信的第二端子。
-
8.发明授权Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations 有权数字接口，用于快速，在线，统计表征过程，MOS器件和电路变化公开(公告)号：US08587288B2
公开(公告)日：2013-11-19
申请号：US12823984
申请日：2010-06-25
申请人： Azeez Jennudin Bhavnagarwala , Stephen V. Kosonocky , Carl John Radens , Kevin Geoffrey Stawiasz
发明人： Azeez Jennudin Bhavnagarwala , Stephen V. Kosonocky , Carl John Radens , Kevin Geoffrey Stawiasz
IPC分类号： G01R31/3187
CPC分类号： G01R31/3004
摘要： A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of
摘要翻译： 提供了一种用于快速准确地统计表征CMOS工艺结构，MOS器件和电路参数的电气特性变化的电路架构和方法。 所提出的电路架构和方法使得在<2mV或<1nA分辨率的测试设备的电压或电流变化的分辨率精度下<1ms / DC扫描的统计特征吞吐量。 提出的电路架构的显着特征包括一个可激励被测器件的可编程斜坡电压发生器，一个双输入9-11位循环ADC，用于捕获输入和输出来自被测器件的直流电压/电流信号，一个2 Kb的锁存器 存储器，以可编程粒度的直流扫描为每个测量点捕获9-11位流，以及时钟和控制方案，其能够连续测量和流出数字数据块，从该模块重新测量被测器件的模拟特性 。
-
9.发明授权Ring power gating with distributed currents using non-linear contact placements 有权使用非线性触点放置的分布电流的环形电源门控公开(公告)号：US08561004B2
公开(公告)日：2013-10-15
申请号：US12758525
申请日：2010-04-12
申请人： Stephen V. Kosonocky
发明人： Stephen V. Kosonocky
CPC分类号： H01L27/0207 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.
摘要翻译： 功率门包括沿着集成电路的至少一部分的一系列电触点和电耦合到集成电路上的电触点的一系列功率栅极晶体管，以形成例如集成电路外围的功率门边界。 沿着电源栅极边界的运行长度的至少一部分的电触点限定了基本上非线性的轮廓。 非线性轮廓提供增加的接触密度，其改善电触头之间的电流平衡和通过功率门的电流吞吐量。 非线性轮廓是具有中间偏移碰撞触点的正弦曲线或锯齿形图案。 沿着功率门边界的接触曲线可以包括线性和非线性轮廓。
-
公开(公告)号：US20120126847A1
公开(公告)日：2012-05-24
申请号：US12950584
申请日：2010-11-19
IPC分类号： G01R31/40
CPC分类号： G01R31/40
摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.
摘要翻译： 通过逐周期监测环形振荡器的性能来测量电源变化和抖动。 通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。 计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。 基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。
-
-
-
-
-
-
-
-
-
搜索结果
59 条记录 (耗时 0.038 秒)
