公开(公告)号：US20120261771A1

公开(公告)日：2012-10-18

申请号：US13088663

申请日：2011-04-18

Applicant: Reinaldo A. VEGA ,  Hongwen YAN

Inventor： Reinaldo A. VEGA ,  Hongwen YAN

IPC: H01L29/772 ,  G06F17/50 ,  H01L21/336

CPC classification number: H01L29/66628 ,  H01L21/02112 ,  H01L21/0226 ,  H01L23/12 ,  H01L29/6653 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.

Abstract translation: 本文提供具有双沟槽区域的半导体结构和制造半导体结构的方法。 该方法包括在有源区上形成栅极结构，并形成在与有源区相邻的一个或多个沟槽中的高k电介质材料。 该方法还包括在有源区域上形成牺牲材料，并且在有源区域的邻近侧壁的高k电介质材料的部分上形成牺牲材料。 该方法还包括去除高k电介质材料的未受保护的部分，在有源区的侧壁上留下高k电介质材料的衬垫。 该方法还包括去除牺牲材料并形成与栅极结构的侧壁相邻的凸起的源极和漏极区域。

公开(公告)号：US20130069160A1

公开(公告)日：2013-03-21

申请号：US13233058

申请日：2011-09-15

Applicant: Michael V. AQUILINO ,  Reinaldo A. VEGA

Inventor： Michael V. AQUILINO ,  Reinaldo A. VEGA

IPC: H01L21/336 ,  H01L29/78 ,  B82Y40/00

CPC classification number: H01L29/66636 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

Abstract: A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.

Abstract translation: 公开了形成沟槽隔离结构的沟槽隔离结构和方法。 该方法包括形成具有突出端并形成栅叠层的浅沟槽隔离（STI）结构。 该方法还包括形成与STI结构和栅极堆叠相邻的源极和漏极凹部。 源极和漏极凹槽通过衬底材料与STI结构分离。 该方法还包括通过用应力源材料填充源极和漏极凹陷来形成与栅极堆叠相关联的外延源极和漏极区域。

公开(公告)号：US20140061862A1

公开(公告)日：2014-03-06

申请号：US13597799

申请日：2012-08-29

Applicant: Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

Inventor： Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

IPC: H01L29/161 ,  H01L21/20

CPC classification number: H01L21/76281 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76208 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

Abstract translation: 提供了包括第一外延半导体层的半导体衬底。 第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。 包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。 包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。 至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。 第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。