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    Forming facet-less epitaxy with self-aligned isolation
    1.
    发明授权
    Forming facet-less epitaxy with self-aligned isolation 有权
    用自对准隔离形成无面外延

    公开(公告)号：US08969163B2

    公开(公告)日：2015-03-03

    申请号：US13556406

    申请日：2012-07-24

    Applicant: Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    Inventor： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/70

    CPC classification number: H01L21/76232 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

    Abstract translation: 形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。 第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。 第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。 使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。 沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

    Semiconductor fin on local oxide
    5.
    发明授权
    Semiconductor fin on local oxide 有权
    半导体翅片局部氧化物

    公开(公告)号：US09035430B2

    公开(公告)日：2015-05-19

    申请号：US13597799

    申请日：2012-08-29

    Applicant: Reinaldo A. Vega ,  Michael V. Aquilino ,  Daniel J. Jaeger

    Inventor： Reinaldo A. Vega ,  Michael V. Aquilino ,  Daniel J. Jaeger

    IPC: H01L21/02 ,  H01L21/308 ,  H01L21/32 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/76281 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76208 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

    Abstract translation: 提供了包括第一外延半导体层的半导体衬底。 第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。 包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。 包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。 至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。 第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

    Trench isolation structure
    7.
    发明授权
    Trench isolation structure 有权
    沟槽隔离结构

    公开(公告)号：US08623713B2

    公开(公告)日：2014-01-07

    申请号：US13233058

    申请日：2011-09-15

    Applicant: Michael V. Aquilino ,  Reinaldo A. Vega

    Inventor： Michael V. Aquilino ,  Reinaldo A. Vega

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/66636 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

    Abstract: A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.

    Abstract translation: 公开了形成沟槽隔离结构的沟槽隔离结构和方法。 该方法包括形成具有突出端并形成栅叠层的浅沟槽隔离（STI）结构。 该方法还包括形成与STI结构和栅极堆叠相邻的源极和漏极凹部。 源极和漏极凹槽通过衬底材料与STI结构分离。 该方法还包括通过用应力源材料填充源极和漏极凹陷来形成与栅极堆叠相关联的外延源极和漏极区域。

    SEMICONDUCTOR FIN ON LOCAL OXIDE
    9.
    发明申请
    SEMICONDUCTOR FIN ON LOCAL OXIDE 有权
    当地氧化物半导体FIN

    公开(公告)号：US20140061862A1

    公开(公告)日：2014-03-06

    申请号：US13597799

    申请日：2012-08-29

    Applicant: Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

    Inventor： Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

    IPC: H01L29/161 ,  H01L21/20

    CPC classification number: H01L21/76281 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76208 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

    Abstract translation: 提供了包括第一外延半导体层的半导体衬底。 第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。 包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。 包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。 至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。 第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

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