公开(公告)号：US20150339201A1

公开(公告)日：2015-11-26

申请号：US14705127

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Nobuyasu KANEKAWA ,  Hitoshi ARIMITSU ,  Takashi YASUMASU ,  Hideki MATSUYAMA

IPC: G06F11/20

CPC classification number: G06F11/2053 ,  G06F11/1616 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/187 ,  G06F2201/85

Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Abstract translation: 本发明提供一种微控制器，即使在故障时也可以继续操作，而不使存储器冗余以抑制芯片面积的增加。 微控制器包括并行执行相同处理的三个或更多个处理器和存储设备。 存储装置包括具有不冗余的存储区域，地址选择部分，数据输出部分和故障恢复部分的存储器垫。 地址选择部分基于处理器访问时发出的三个或更多个地址来选择存储器存储器中的存储区域。 数据输出部分从由地址选择部分选择的存储器堆中的存储区域读取数据。 故障恢复部件校正或掩蔽发生在存储器垫，地址选择部分和数据输出部分中的预定数量或更少的故障。

公开(公告)号：US20150113248A1

公开(公告)日：2015-04-23

申请号：US14584778

申请日：2014-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki MATSUYAMA

IPC: G06F13/24 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/461 ,  G06F9/462 ,  G06F9/48

Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Abstract translation: 微型计算机包括：分别具有多个寄存器模式的多个寄存器列表，其中多个寄存器模式中的每一个指定寄存器，其数据将被保存在数据存储器中; 指令获取控制电路，被配置为响应于基于中断因素的发生而发出的中断请求，从指令存储器取出指令代码; 以及寄存器数据保存控制电路，配置为响应于所述中断请求从所述多个寄存器列表中的一个寄存器列表获取一个寄存器模式，并且响应于所述中断请求，基于所获取的寄存器模式发出微指令。 指令执行部分被配置为在获取的指令代码之前执行微指令，以将基于所获取的寄存器模式指定的寄存器的数据保存在数据存储器中。