公开(公告)号：US20160079426A1

公开(公告)日：2016-03-17

申请号：US14952782

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Hiroshi TAKEDA ,  Toshiharu NAGUMO ,  Takashi HASE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

公开(公告)号：US20160049375A1

公开(公告)日：2016-02-18

申请号：US14925584

申请日：2015-10-28

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Takashi ONIZAWA ,  Takashi HASE ,  Shigeru HIRAO ,  Tadatoshi DANNO

IPC: H01L23/00 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3178 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.

Abstract translation: 半导体器件包括包括第一面的衬底。 该器件还包括缓冲层，半导体层，源极和漏极以及栅电极。 在半导体层上形成沟槽，使得沟槽在平面图中围绕源电极，漏电极和栅电极，沟槽穿过半导体层和缓冲层，并且沟槽的底部到达 至少衬底的内部。 从衬底的第一面到沟槽的底部的距离在衬底的厚度方向上为100nm以上。