公开(公告)号：US20160049375A1

公开(公告)日：2016-02-18

申请号：US14925584

申请日：2015-10-28

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Takashi ONIZAWA ,  Takashi HASE ,  Shigeru HIRAO ,  Tadatoshi DANNO

IPC: H01L23/00 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3178 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.

Abstract translation: 半导体器件包括包括第一面的衬底。 该器件还包括缓冲层，半导体层，源极和漏极以及栅电极。 在半导体层上形成沟槽，使得沟槽在平面图中围绕源电极，漏电极和栅电极，沟槽穿过半导体层和缓冲层，并且沟槽的底部到达 至少衬底的内部。 从衬底的第一面到沟槽的底部的距离在衬底的厚度方向上为100nm以上。

公开(公告)号：US20130168690A1

公开(公告)日：2013-07-04

申请号：US13734844

申请日：2013-01-04

Applicant: Renesas Electronics Corporation

Inventor： Nobuyuki IKARASHI ,  Takashi ONIZAWA ,  Motofumi SAITOH

IPC: H01L29/778

CPC classification number: H01L21/02178 ,  H01L21/28264 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66659 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7835

Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.

Abstract translation: 第一氮化物半导体层含有Ga，第一氮化物半导体层例如为GaN层，AlGaN层，AlInGaN层。 然后，氧化铝层具有四个配位的Al原子，每个四个配位的Al原子被四个O原子和六配位的Al原子包围，六个O原子围绕着相对于第一氮化物半导体层的界面区域中的Al原子。 界面区域是从相对于第一氮化物半导体层的界面分开例如1.5nm以下的区域。 然后，在界面区域中，四配位Al原子相对于Al原子总数为30原子％以上且小于50原子％。