公开(公告)号：US20160079426A1

公开(公告)日：2016-03-17

申请号：US14952782

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Hiroshi TAKEDA ,  Toshiharu NAGUMO ,  Takashi HASE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

公开(公告)号：US20130214348A1

公开(公告)日：2013-08-22

申请号：US13766202

申请日：2013-02-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi TAKEDA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a vertical transistor, to raise a drain withstand voltage while lowering an on-resistance. A drift layer 120 is formed above a drain layer 110, and has a first conductivity type. A gate insulating film 170 is formed on a side wall of a concave portion 142. A bottom surface insulating film 172 is formed on a bottom surface of the concave portion 142. A gate electrode 180 is buried in the concave portion 142. A source layer 150 is formed in a channel layer 140. A first conductivity type layer 130 is located between the channel layer 140 and the drift layer 120. An impurity concentration of the first conductivity type layer 130 is higher than an impurity concentration of the drift layer 120.

Abstract translation: 在垂直晶体管中，提高漏极耐受电压同时降低导通电阻。 漂移层120形成在漏极层110的上方，并且具有第一导电类型。 栅极绝缘膜170形成在凹部142的侧壁上。底面绝缘膜172形成在凹部142的底面上。栅电极180埋设在凹部142中。源极层 150形成在沟道层140中。第一导电类型层130位于沟道层140和漂移层120之间。第一导电类型层130的杂质浓度高于漂移层120的杂质浓度。

公开(公告)号：US20130105813A1

公开(公告)日：2013-05-02

申请号：US13666507

申请日：2012-11-01

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi TAKEDA

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/20

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/785

Abstract: Disclosed is a semiconductor device whose breakdown voltage is made high by controlling local concentration of an electric field. A source region faces a second plane, one of side faces of a groove part, and a part thereof extends in a direction in parallel to a nodal line of first and second planes. A drift region faces a third plane being the other side face of the groove part opposite to the second plane with a part thereof extending in a direction parallel to the nodal line of the first plane and the third plane, and is formed at a lower concentration than the source region. The drain region is provided so as to be placed on the other side of the drift region opposite to the groove part and so as to touch the drift region, and is formed at a higher concentration than the drift region.

Abstract translation: 公开了通过控制电场的局部浓度使击穿电压变高的半导体装置。 源区域面向第二平面，凹槽部分的一个侧面，并且其一部分在平行于第一和第二平面的节点线的方向上延伸。 漂移区域面向与第二平面相对的槽部的另一侧面的第三平面，其一部分在与第一平面和第三平面的节点平行的方向上延伸，并且形成为较低的浓度 比源区域。 漏极区域设置成位于漂移区域的与沟槽部分相对的另一侧并且与漂移区域接触，并且形成在比漂移区域更高的浓度处。