公开(公告)号：US20140002147A1

公开(公告)日：2014-01-02

申请号：US13929365

申请日：2013-06-27

Applicant: Renesas Electronics Corporation

Inventor： Tomoki YASUKAWA ,  Kazuyoshi KAWAI

IPC: H03K3/011

CPC classification number: H03K3/011 ,  G06F13/1689 ,  H03K5/156

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract translation: 操作时钟生成电路基于基本时钟的频率误差和基本时钟的时钟脉冲进行计算，并且生成通过以第一间隔校正频率误差而获得的操作时钟。 校正时钟产生电路将作为将用于判断操作时钟的状态的改变的预定位的比特所表示的值转换为频率为第二时钟的时钟脉冲的计数次数的低位值 高于操作时钟的时钟，产生通过基于计数时钟脉冲的计数和操作时钟的时钟脉冲所需的时间来校正操作时钟而获得的校正时钟。

公开(公告)号：US20180143229A1

公开(公告)日：2018-05-24

申请号：US15796995

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Makoto SHUTO ,  Kazuyoshi KAWAI ,  Mitsuya FUKAZAWA ,  Robert NOLF ,  Robert DALBY

IPC: G01R21/133 ,  H03G3/20 ,  H03M3/00 ,  H03M1/38 ,  G01R19/252

CPC classification number: G01R21/133 ,  G01R19/252 ,  H03G3/20 ,  H03H17/0621 ,  H03M1/1205 ,  H03M1/38 ,  H03M3/458

Abstract: There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.

公开(公告)号：US20140333349A1

公开(公告)日：2014-11-13

申请号：US14340044

申请日：2014-07-24

Applicant: Renesas Electronics Corporation

Inventor： Tomoki YASUKAWA ,  Kazuyoshi KAWAI

IPC: H03K3/011

CPC classification number: H03K3/011 ,  G06F13/1689 ,  H03K5/156

Abstract: An operation clock generation circuit performs calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract translation: 操作时钟生成电路基于基本时钟的频率误差和基本时钟的时钟脉冲进行计算，并且生成通过以第一间隔校正频率误差而获得的操作时钟。 校正时钟产生电路将作为将用于判断操作时钟的状态的改变的预定位的比特所表示的值转换为频率为第二时钟的时钟脉冲的计数次数的低位值 高于操作时钟的时钟，产生通过基于计数时钟脉冲的计数和操作时钟的时钟脉冲所需的时间来校正操作时钟而获得的校正时钟。