公开(公告)号：US20160065001A1

公开(公告)日：2016-03-03

申请号：US14843823

申请日：2015-09-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoki YASUKAWA ,  Akira OIZUMI ,  Toyohiko YOSHIDA ,  Yoshinori TOKIOKA

IPC: H02J9/06

CPC classification number: H02J9/061 ,  H02J1/10

Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.

Abstract translation: 所公开的发明旨在防止内部电路的故障，因为在由备用电源供电的半导体器件的操作期间由噪声引起的不期望的电源切换，同时消除备用电源的浪费的消耗。 在将备用电源端子连接到内部电源节点之后，将备用电源端子与内部电源节点解耦之前，将主电源端子耦合到内部电源节点之后的第一切换转换时间比第二切换时间长 电源节点，直到主电源端子与内部电源节点断开。

公开(公告)号：US20140333349A1

公开(公告)日：2014-11-13

申请号：US14340044

申请日：2014-07-24

Applicant: Renesas Electronics Corporation

Inventor： Tomoki YASUKAWA ,  Kazuyoshi KAWAI

IPC: H03K3/011

CPC classification number: H03K3/011 ,  G06F13/1689 ,  H03K5/156

Abstract: An operation clock generation circuit performs calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract translation: 操作时钟生成电路基于基本时钟的频率误差和基本时钟的时钟脉冲进行计算，并且生成通过以第一间隔校正频率误差而获得的操作时钟。 校正时钟产生电路将作为将用于判断操作时钟的状态的改变的预定位的比特所表示的值转换为频率为第二时钟的时钟脉冲的计数次数的低位值 高于操作时钟的时钟，产生通过基于计数时钟脉冲的计数和操作时钟的时钟脉冲所需的时间来校正操作时钟而获得的校正时钟。

公开(公告)号：US20140002147A1

公开(公告)日：2014-01-02

申请号：US13929365

申请日：2013-06-27

Applicant: Renesas Electronics Corporation

Inventor： Tomoki YASUKAWA ,  Kazuyoshi KAWAI

IPC: H03K3/011

CPC classification number: H03K3/011 ,  G06F13/1689 ,  H03K5/156

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract translation: 操作时钟生成电路基于基本时钟的频率误差和基本时钟的时钟脉冲进行计算，并且生成通过以第一间隔校正频率误差而获得的操作时钟。 校正时钟产生电路将作为将用于判断操作时钟的状态的改变的预定位的比特所表示的值转换为频率为第二时钟的时钟脉冲的计数次数的低位值 高于操作时钟的时钟，产生通过基于计数时钟脉冲的计数和操作时钟的时钟脉冲所需的时间来校正操作时钟而获得的校正时钟。

公开(公告)号：US20180006491A1

公开(公告)日：2018-01-04

申请号：US15702354

申请日：2017-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoki YASUKAWA ,  Akira OIZUMI ,  Toyohiko YOSHIDA ,  Yoshinori TOKIOKA

IPC: H02J9/06 ,  H02J1/10

CPC classification number: H02J9/061 ,  H02J1/10

Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.