公开(公告)号：US20250015200A1

公开(公告)日：2025-01-09

申请号：US18666131

申请日：2024-05-16

Applicant: Renesas Electronics Corporation

Inventor： Keiichi FURUYA

IPC: H01L29/866 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66

Abstract: A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.

公开(公告)号：US20230099677A1

公开(公告)日：2023-03-30

申请号：US17944678

申请日：2022-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keiichi FURUYA

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/265 ,  H01L21/266 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface, a plurality of wirings which are layered over the first main surface in a thickness direction that is a direction extending from the second main surface to the first main surface, and a passivation film which covers a top wiring that is a wiring being at a farthest position from the first main surface in the thickness direction, of the plurality of wirings. The top wiring has a first linear portion linearly extending along a first direction from a termination portion of the top wiring. The passivation film has a first dummy opening, the first dummy opening penetrating the passivation film in the thickness direction. The first dummy opening is disposed so as to overlap with an end portion of the first linear portion on the termination portion side, in plan view.

公开(公告)号：US20170186864A1

公开(公告)日：2017-06-29

申请号：US15378256

申请日：2016-12-14

Applicant: Renesas Electronics Corporation

Inventor： Keiichi FURUYA

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/40 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L29/7823 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0617 ,  H01L27/0623 ,  H01L27/088 ,  H01L28/00 ,  H01L28/10 ,  H01L29/0649 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7819

Abstract: A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.