公开(公告)号：US20160365443A1

公开(公告)日：2016-12-15

申请号：US15182120

申请日：2016-06-14

申请人： Infineon Technologies AG

发明人： Andreas Meiser ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

摘要翻译： 晶体管单元包括与源极区域横向间隔开的漂移区域，源极区域，体区域和漏极区域。 栅电极与身体区域相邻。 场漂移区域设置场电极。 源电极连接到源极区域和主体区域，并且漏电极连接到漏极区域。 雪崩旁路结构耦合在源电极和漏极之间，并且包括第一掺杂型的第一半导体层，第一掺杂型的第二半导体层和布置在第一半导体层和源极之间的pn结 电极。 第二半导体层具有比第一半导体层更高的掺杂浓度，并且布置在第二半导体层和漂移区之间。 漏极电连接到第二半导体层。

公开(公告)号：US20160211256A1

公开(公告)日：2016-07-21

申请号：US14987528

申请日：2016-01-04

申请人： SEIKO INSTRUMENTS INC.

发明人： Kazuhiro TSUMURA

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L29/78

CPC分类号： H01L27/0629 ,  G01K7/01 ,  H01L23/34 ,  H01L28/20 ,  H01L29/78 ,  H01L29/7819

摘要： A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a PN junction of the temperature sensing element is connected to a ground potential (VSS) or a power supply potential (VDD) through an intermediation of a resistor. A sum of a potential difference between both ends of the PN junction and a potential difference between both ends of the resistor is used as a temperature detection signal. The temperature sensing element can thus be formed in a recess formed in the power element while avoiding latch-up.

摘要翻译： 功率元件和温度感测元件形成在相同的半导体衬底上，并且温度感测元件的PN结的一端通过一个接地电位（VSS）或电源电位（VDD）连接到接地电位（VSS）或电源电位（VDD） 电阻。 作为温度检测信号，使用PN结的两端之间的电位差与电阻两端的电位差之和。 因此，温度感测元件可以形成在功率元件中形成的凹部中，同时避免闩锁。

公开(公告)号：US08890252B2

公开(公告)日：2014-11-18

申请号：US13190798

申请日：2011-07-26

申请人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

发明人： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

IPC分类号： H01L21/70 ,  H01L21/78 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/861 ,  H02M7/00

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

摘要翻译： 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

公开(公告)号：US07723780B2

公开(公告)日：2010-05-25

申请号：US12122964

申请日：2008-05-19

申请人： Sung-Man Pang

发明人： Sung-Man Pang

IPC分类号： H01L29/94

CPC分类号： H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

摘要： A lateral DMOS device includes a body diode region and a protective diode region. The body diode region has a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well region including a first conduction type body region and a drain region each formed in the second conduction type well region, a first conduction type impurity region and a source region formed in the first conduction type body region, and a gate insulating film and a gate electrode formed on the first conduction type semiconductor substrate. The first conduction type body region and the second conduction type well region compose a body diode. In the protective diode region, the first conduction type impurity region is formed at a prescribed interval and the first conduction type body region and the second conduction type well region compose a protective diode.

摘要翻译： 横向DMOS器件包括体二极管区域和保护二极管区域。 体二极管区域具有形成在第一导电型半导体衬底中的第二导电类型阱区域，第二导电类型阱区域包括分别形成在第二导电类型阱区域中的第一导电类型体区域和漏极区域，第一导电 形成在第一导电型体区中的源区，以及形成在第一导电型半导体衬底上的栅极绝缘膜和栅电极。 第一导电类型体区域和第二导电类型阱区域构成体二极管。 在保护二极管区域中，以规定间隔形成第一导电型杂质区域，第一导电型体区域和第二导电型阱区域构成保护二极管。

公开(公告)号：US11705485B2

公开(公告)日：2023-07-18

申请号：US17543279

申请日：2021-12-06

申请人： Maxim Integrated Products, Inc.

发明人： Vijay Parthasarathy ,  Vipindas Pala ,  Marco A. Zuniga

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H02M3/158

CPC分类号： H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7819 ,  H02M3/158

摘要： A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

公开(公告)号：US20170221876A1

公开(公告)日：2017-08-03

申请号：US15484143

申请日：2017-04-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

摘要： An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

公开(公告)号：US09673320B2

公开(公告)日：2017-06-06

申请号：US15182120

申请日：2016-06-14

申请人： Infineon Technologies AG

发明人： Andreas Meiser ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

公开(公告)号：US20170110446A1

公开(公告)日：2017-04-20

申请号：US14938850

申请日：2015-11-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

摘要： An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

公开(公告)号：US09293578B2

公开(公告)日：2016-03-22

申请号：US13935264

申请日：2013-07-03

申请人： Hitachi, Ltd.

发明人： Tomoyuki Miyoshi ,  Takayuki Oshima ,  Yohei Yanagida ,  Hiroki Kimura ,  Kenji Miyakoshi

IPC分类号： H01L29/66 ,  H01L21/332 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/7818 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7819 ,  H01L29/7835

摘要： Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region of the first semiconductor region is formed at a distance from the field oxide film near an end portion remote from the gate electrode, and desirably the feeding region is intermittently formed at intervals in the longitudinal direction.

摘要翻译： 对LDMOSFET的电流性能几乎不产生不利影响，以抑制来自LDMOS寄生二极管的阳极层的载流子注入量，并提高寄生二极管的反向恢复耐受性。 LDMOSFET包括半导体衬底，该半导体衬底具有第一半导体区域，该第一半导体区域由选择性地形成场氧化膜的半导体区域的表面层上不存在场氧化物膜的位置处形成有第一导电类型的馈电区域， 以及第二半导体区域，由与导电类型相反的第二导电类型的阱区域形成，并且形成在阱区的上层上的第一导电类型和第二导电类型的馈电区域以及栅电极， 通过栅极氧化膜面对阱区。 第一半导体区域的馈电区域形成在远离栅电极的端部附近的场氧化膜的距离处，并且期望地沿纵向方向间隔地形成馈送区域。

公开(公告)号：US20230421072A1

公开(公告)日：2023-12-28

申请号：US18331735

申请日：2023-06-08

申请人： ROHM CO., LTD.

发明人： Satoki TANIGUCHI ,  Kentaro NASU

IPC分类号： H02M7/217 ,  H01L27/092 ,  H01L27/088 ,  H01L27/06

CPC分类号： H02M7/217 ,  H01L27/092 ,  H01L27/088 ,  H01L27/0629 ,  H01L29/7819

摘要： A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.