公开(公告)号：US09159807B2

公开(公告)日：2015-10-13

申请号：US14220643

申请日：2014-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Komaki Inoue ,  Yutaka Hoshino

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/74 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

Abstract translation: 提高了在SOI衬底上形成的MOSFET的半导体器件的可靠性。 半导体器件的制造方法简化。 在SOI衬底SB上形成的具有n沟道MOSFET Qn的半导体器件包括在BOX膜下形成为在支撑衬底的上表面上的扩散层的n +型半导体区域，以及与n + 并且穿透可以控制支撑衬底的电位的元件隔离区域。 在SOI衬底SB的平面上，n沟道MOSFETsn各自沿第一方向延伸，并且布置在沿第一方向彼此相邻形成的接触插头CT2之间。

公开(公告)号：US10790388B2

公开(公告)日：2020-09-29

申请号：US16036434

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Makoto Koshimizu ,  Komaki Inoue ,  Hideki Niwayama

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/324 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285

Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.